On Mon, Feb 10, 2020 at 5:33 AM Mihailo Stojanovic <mihailo.stojano...@rt-rk.com> wrote: > > Similar to the mirror case of allocating an FPR for an integer mode > pseudo, prevent GPRs from being allocated for a floating mode pseudo.
Can you expand on why you want to do this? Provide benchmarking or a testcase which this improves the code generation? I can see this producing much worse code for soft-float (which I still care about). Thanks, Andrew Pinski > > gcc/ChangeLog: > > * gcc/config/mips/mips.c (mips_ira_change_pseudo_allocno_class): > Limit the allocation of floating mode pseudos to FP_REGS. > --- > gcc/config/mips/mips.c | 6 ++++++ > 1 file changed, 6 insertions(+) > > diff --git a/gcc/config/mips/mips.c b/gcc/config/mips/mips.c > index 513fc5f..ffcb14d 100644 > --- a/gcc/config/mips/mips.c > +++ b/gcc/config/mips/mips.c > @@ -22492,6 +22492,12 @@ mips_ira_change_pseudo_allocno_class (int regno, > reg_class_t allocno_class, > instructions that say integer mode values must be placed in FPRs. */ > if (INTEGRAL_MODE_P (PSEUDO_REGNO_MODE (regno)) && allocno_class == > ALL_REGS) > return GR_REGS; > + > + /* Likewise for the mirror case of floating mode pseudos being allocated in > + a GPR. */ > + if (FLOAT_MODE_P (PSEUDO_REGNO_MODE (regno)) && allocno_class == ALL_REGS) > + return FP_REGS; > + > return allocno_class; > } > > -- > 2.7.4 >
