On Fri, Jan 31, 2020 at 10:56:10AM -0600, Bill Schmidt wrote:
> On 1/31/20 9:42 AM, Segher Boessenkool wrote:
> >On Fri, Jan 31, 2020 at 08:49:21AM -0600, Bill Schmidt wrote:
> >>>+(define_register_constraint "wa"
> >>>"rs6000_constraints[RS6000_CONSTRAINT_wa]"
> >>>+ "A VSX register (VSR), @code{vs0}@dots{}@code{vs63}. Either a
> >>>@code{d}
> >>>+ or a @code{v} register.")
> >>Not quite true, as the "d" register is only half of a VSX register. It
> >>may or may not be worth including a picture of register overlaps...
> >No, the "d" registers are the actual full registers, all 128 bits of it.
> >You often use them in a mode that uses only 64 bits, sure.
>
> Perhaps that would be worth a few words when describing the "d"
> constraint, then. This is not at all obvious to the casual user. Thanks!
"They should read the ISA, it's all explained right at the start of
Chapter 7".
"All instructions that operate on an FPR are redefined to operate on
doubleword element 0 of the corresponding VSR. The contents of
doubleword element 1 of the VSR corresponding to a source FPR or FPR
pair for these instructions are ignored and the contents of doubleword
element 1 of the VSR corresponding to the target FPR or FPR pair for
these instructions are undefined."
The twist in GCC is that all register numbers always denote the whole
register. Compares this to (reg:DI 3) vs. (reg:SI 3) (and even HI and
QI); here it is (reg:DF 32) vs. (reg:V2DF 32) (etc.)
None of the VSRs are separate registers, they just *are* the FPRs and
the VRs. On the machines the FPRs are in some implementations really
only half the width of the VSRs, or the other half does not even exist
on older machines; but inside GCC, such details do not matter.
But I'll add some more words, sure, it is probably useful to explain
some of the basic setup :-)
The tricky part is to have it make sense when you read it in order, but
to also make sense when used as a reference.
Segher
