On 11/19/19 2:02 AM, Claudiu Zissulescu wrote: > ARC processors can use scaled addresses, i.e., the offset part of the > load address can be shifted by 2 (multiplied by 4). Add this pattern > and a test for it. > > gcc/ > xxxx-xx-xx Claudiu Zissulescu <claz...@synopsys.com> > > * config/arc/arc.md (load_scaledsi): New pattern. > > testcase/ > xxxx-xx-xx Claudiu Zissulescu <claz...@synopsys.com> > > * gcc.target/arc/scaled-ld.c: New test. This is worrisome. I'm pretty sure this has to be folded into the existing move pattern to satisfy obscure reload requirements.
Jeff
