On 11/19/19 4:19 AM, Richard Biener wrote:
On Tue, Nov 19, 2019 at 10:04 AM Jakub Jelinek <ja...@redhat.com> wrote:
Hi!
xchg instruction is smaller, in some cases much smaller than 3 moves,
(e.g. in the testcase 2 bytes vs. 8 bytes), and is not a performance
disaster, but from Agner Fog tables and
https://stackoverflow.com/questions/45766444/why-is-xchg-reg-reg-a-3-micro-op-instruction-on-modern-intel-architectures
it doesn't seem to be something we'd want to use when optimizing for speed,
at least not on Intel.
While we have *swap<mode> patterns, those are very unlikely to be triggered
during combine, usually we have different pseudos in there and the actual
need for swapping is only materialized during RA.
The following patch does it when optimizing the insn for size only.
Bootstrapped/regtested on x86_64-linux and i686-linux, ok for trunk?
I wonder if IRA/LRA should be made aware of an xchg instruction
(and it's cost?) so it knows it doesn't actually need a temporary register?
There is one place where it could be used. It is
ira-emit.c::modify_move_list where register shuffling on region border
happens. It is possible that pseudo1:hr1, pseudo2:hr2 inside a region
should be pseudo1:hr2 and pseudo2:hr1 outside the region.
First I used a trick of 3 xor insns to break cycle w/o new temp
creation. But such move cycles were so very rare events that I just
finished with new temp creation. That is extremely rare case, the goal
IRA to decrease any move generation on region borders. But if somebody
implements xchg usage there, I'll not be against this.
