Hi Richard,
> except we can do better than this...
> (see below). With that change, this just becomes <LOGICAL:optab>di3
>> +(define_code_attr logical_op [(ior "ior") (xor "xor") (and "and")])
>
> These should just be added to the existing 'optab' attribute, there's no
> need for an additional attribute.
>> +(define_code_attr logical_OP [(ior "IOR") (xor "XOR") (and "AND")])
>
> You don't need this, just use <CODE> where you want this substitution.
Yes we can avoid the new code attributes indeed and add to the existing
optab one. Here is what I did:
[PATCH][ARM] Simplify logical DImode iterators
Further simplify the logical DImode expander using code iterator and
obtab attributes. This avoids adding unnecessary code_attr entries.
ChangeLog:
2019-09-19 Wilco Dijkstra <wdijk...@arm.com>
* config/arm/arm.md (<logical_op>di3): Use <optab> and <CODE>.
* config/arm/iterators.md (optab): Add and, ior, xor entries.
(logical_op): Remove code attribute.
(logical_OP): Likewise.
--
diff --git a/gcc/config/arm/arm.md b/gcc/config/arm/arm.md
index
d54082b13dd702aa55a1465c0fbfa87baa89149a..d607f88cb05ffa9cd8a47b8c8e0c53ea3a5ca411
100644
--- a/gcc/config/arm/arm.md
+++ b/gcc/config/arm/arm.md
@@ -2039,16 +2039,16 @@ (define_expand "divdf3"
; operands or complex immediates, which leads to fewer LDRD/STRD instructions.
; So an explicit expander is needed to generate better code.
-(define_expand "<logical_op>di3"
+(define_expand "<LOGICAL:optab>di3"
[(set (match_operand:DI 0 "s_register_operand")
(LOGICAL:DI (match_operand:DI 1 "s_register_operand")
- (match_operand:DI 2 "arm_<logical_op>di_operand")))]
+ (match_operand:DI 2 "arm_<optab>di_operand")))]
"TARGET_32BIT"
{
- rtx low = simplify_gen_binary (<logical_OP>, SImode,
+ rtx low = simplify_gen_binary (<CODE>, SImode,
gen_lowpart (SImode, operands[1]),
gen_lowpart (SImode, operands[2]));
- rtx high = simplify_gen_binary (<logical_OP>, SImode,
+ rtx high = simplify_gen_binary (<CODE>, SImode,
gen_highpart (SImode, operands[1]),
gen_highpart_mode (SImode, DImode,
operands[2]));
diff --git a/gcc/config/arm/iterators.md b/gcc/config/arm/iterators.md
index
5e3299e850813db2f3c0a25a6cde779d1d0d1d55..98ded4b22b2885e77e0ea0f1ce73ed12845115d3
100644
--- a/gcc/config/arm/iterators.md
+++ b/gcc/config/arm/iterators.md
@@ -287,9 +287,6 @@ (define_code_attr cmp_type [(eq "i") (gt "s") (ge "s") (lt
"s") (le "s")])
(define_code_attr vfml_op [(plus "a") (minus "s")])
-(define_code_attr logical_op [(ior "ior") (xor "xor") (and "and")])
-(define_code_attr logical_OP [(ior "IOR") (xor "XOR") (and "AND")])
-
;;----------------------------------------------------------------------------
;; Int iterators
;;----------------------------------------------------------------------------
@@ -797,7 +794,7 @@ (define_code_attr VQH_sign [(plus "i") (smin "s") (smax
"s") (umin "u")
(umax "u")])
(define_code_attr cnb [(ltu "CC_C") (geu "CC")])
-(define_code_attr optab [(ltu "ltu") (geu "geu")])
+(define_code_attr optab [(ltu "ltu") (geu "geu") (and "and") (ior "ior") (xor
"xor")])
;; Assembler mnemonics for signedness of widening operations.
(define_code_attr US [(sign_extend "s") (zero_extend "u")])
