+(define_insn "zero_extendsidi2"
+ [(set (match_operand:DI 0 "register_operand" "=r,r")
+ (zero_extend:DI
+ (match_operand:SI 1 "reg_or_memory_operand" "0,m")))]
+ ""
+ "@
+ mov32\t%0,%1
+ ldxw\t%0,%1"
+ [(set_attr "type" "alu,ldx")])Auto review: the 0 above should be `r'. Fixed for the next version.
