On Tue, Aug 27, 2019 at 02:59:01PM +0200, Jose E. Marchesi wrote: > glglgl, scratch that, it is actually a 32-bit multiplication that then > gets extended to 64-bits: > > (define_insn "*mulsidi3_zeroextended" > [(set (match_operand:DI 0 "register_operand" "=r,r") > (zero_extend:DI > (mult:SI (match_operand:SI 1 "register_operand" "0,0") > (match_operand:SI 2 "reg_or_imm_operand" "r,I"))))] > "" > "mul32\t%0,%2" > [(set_attr "type" "alu32")])
Like pretty much *all* the 32-bit instructions, btw... All of them could have a variant with a zero_extend like this. Something for define_subst, perhaps. On rs6000 we call such patterns "*rotlsi3_64" (where the pure 32-bit one is called "rotlsi3"), maybe you want some similar naming? Something that makes it clearer that it is the same insn as mulsi3. Segher
