The current SIBCALL_REGS are x6, x7, and x28 to x31. These are all
caller saved registers, however, they are not all of the caller saved
registers.
I don't see any reason why we couldn't add t1, and a0 to a7 into this
set, and this is what this patch does.
gcc/ChangeLog:
* config/riscv/riscv.h (REG_CLASS_CONTENTS): Update SIBCALL_REGS.
---
gcc/ChangeLog | 4 ++++
gcc/config/riscv/riscv.h | 2 +-
2 files changed, 5 insertions(+), 1 deletion(-)
diff --git a/gcc/config/riscv/riscv.h b/gcc/config/riscv/riscv.h
index 5fc9be8edbf2..bb8240bb849a 100644
--- a/gcc/config/riscv/riscv.h
+++ b/gcc/config/riscv/riscv.h
@@ -400,7 +400,7 @@ enum reg_class
#define REG_CLASS_CONTENTS \
{ \
{ 0x00000000, 0x00000000, 0x00000000 }, /* NO_REGS */ \
- { 0xf00000c0, 0x00000000, 0x00000000 }, /* SIBCALL_REGS */ \
+ { 0xf003fce0, 0x00000000, 0x00000000 }, /* SIBCALL_REGS */ \
{ 0xffffffc0, 0x00000000, 0x00000000 }, /* JALR_REGS */ \
{ 0xffffffff, 0x00000000, 0x00000000 }, /* GR_REGS */ \
{ 0x00000000, 0xffffffff, 0x00000000 }, /* FP_REGS */ \
--
2.14.5
