SVE defines an assembly alias:
MOV pa.B, pb/Z, pc.B -> AND pa.B. pb/Z, pc.B, pc.B
Our and<mode>3 pattern was instead using the functionally-equivalent:
AND pa.B. pb/Z, pb.B, pc.B
^^^^
This patch duplicates pc.B instead so that the alias can be seen
in disassembly.
I wondered about using the alias in the pattern instead, but using AND
explicitly seems to fit better with the pattern name and surrounding code.
Tested on aarch64-linux-gnu (with and without SVE) and aarch64_be-elf.
Applied as r274521.
Richard
2019-08-15 Richard Sandiford <richard.sandif...@arm.com>
gcc/
* config/aarch64/aarch64-sve.md (and<PRED_ALL:mode>3): Make the
operand order match the MOV /Z alias.
Index: gcc/config/aarch64/aarch64-sve.md
===================================================================
--- gcc/config/aarch64/aarch64-sve.md 2019-08-15 09:47:20.176358327 +0100
+++ gcc/config/aarch64/aarch64-sve.md 2019-08-15 09:54:12.977312970 +0100
@@ -3317,12 +3317,14 @@ (define_insn "*<optab><mode>3"
;; -------------------------------------------------------------------------
;; Predicate AND. We can reuse one of the inputs as the GP.
+;; Doubling the second operand is the preferred implementation
+;; of the MOV alias, so we use that instead of %1/z, %1, %2.
(define_insn "and<mode>3"
[(set (match_operand:PRED_ALL 0 "register_operand" "=Upa")
(and:PRED_ALL (match_operand:PRED_ALL 1 "register_operand" "Upa")
(match_operand:PRED_ALL 2 "register_operand" "Upa")))]
"TARGET_SVE"
- "and\t%0.b, %1/z, %1.b, %2.b"
+ "and\t%0.b, %1/z, %2.b, %2.b"
)
;; Unpredicated predicate EOR and ORR.
