This patch changes the SVE FP<->FP and FP<->INT patterns so that
they use unspecs rather than rtx codes, continuing the series
to make the patterns work with predicates that might not be all-true.
Tested on aarch64-linux-gnu (with and without SVE) and aarch64_be-elf.
Applied as r274423.
Richard
2019-08-14 Richard Sandiford <richard.sandif...@arm.com>
gcc/
* config/aarch64/aarch64.md (UNSPEC_FLOAT_CONVERT): Delete.
* config/aarch64/iterators.md (UNSPEC_COND_FCVT, UNSPEC_COND_FCVTZS)
(UNSPEC_COND_FCVTZU, UNSPEC_COND_SCVTF, UNSPEC_COND_UCVTF): New
unspecs.
(optab, su): Handle them.
(SVE_COND_FCVTI, SVE_COND_ICVTF): New int iterators.
* config/aarch64/aarch64-sve.md
(<fix_trunc_optab><SVE_F:mode><v_int_equiv>2): Replace with...
(<SVE_COND_FCVTI:optab><SVE_F:mode><v_int_equiv>2): ...this.
(*<fix_trunc_optab>v16hsf<:SVE_HSDImode>2): Replace with...
(*<SVE_COND_FCVTI:optab>v16hsf<SVE_F:mode>2): ...this.
(*<fix_trunc_optab>vnx4sf<SVE_SDI:mode>2): Replace with...
(*<SVE_COND_FCVTI:optab>vnx4sf<SVE_SDI:mode>2): ...this.
(*<fix_trunc_optab>vnx2df<SVE_SDI:mode>2): Replace with...
(*<SVE_COND_FCVTI:optab>vnx2df<SVE_SDI:mode>2): ...this.
(vec_pack_<su>fix_trunc_vnx2df): Use SVE_COND_FCVTI instead of
FIXUORS.
(<FLOATUORS:optab><v_int_equiv><SVE_F:mode>2): Replace with...
(<SVE_COND_ICVTF:optab><v_int_equiv><SVE_F:mode>2): ...this.
(*<FLOATUORS:optab><SVE_HSDI:mode>vnx8hf2): Replace with...
(*<SVE_COND_ICVTF:optab><SVE_HSDI:mode>vnx8hf2): ...this.
(*<FLOATUORS:optab><SVE_SDI:mode>vnx4sf2): Replace with...
(*<SVE_COND_ICVTF:optab><SVE_SDI:mode>vnx4sf2): ...this.
(aarch64_sve_<FLOATUORS:optab><SVE_SDI:mode>vnx2df2): Replace with...
(aarch64_sve_<SVE_COND_ICVTF:optab><SVE_SDI:mode>vnx2df2): ...this.
(vec_unpack<su_optab>_float_<perm_hilo>_vnx4si): Pass a GP strictness
operand to aarch64_sve_<SVE_COND_ICVTF:optab><SVE_SDI:mode>vnx2df2.
(vec_pack_trunc_<SVE_HSF:Vwide>, *trunc<Vwide><SVE_HSF:mode>2)
(aarch64_sve_extend<mode><Vwide>2): Use UNSPEC_COND_FCVT instead
of UNSPEC_FLOAT_CONVERT.
(vec_unpacks_<perm_hilo>_<mode>): Pass a GP strictness operand to
aarch64_sve_extend<mode><Vwide>2.
Index: gcc/config/aarch64/aarch64.md
===================================================================
--- gcc/config/aarch64/aarch64.md 2019-08-14 09:15:57.617827961 +0100
+++ gcc/config/aarch64/aarch64.md 2019-08-14 09:32:41.846404780 +0100
@@ -226,7 +226,6 @@ (define_c_enum "unspec" [
UNSPEC_UNPACKSLO
UNSPEC_UNPACKULO
UNSPEC_PACK
- UNSPEC_FLOAT_CONVERT
UNSPEC_WHILE_LO
UNSPEC_LDN
UNSPEC_STN
Index: gcc/config/aarch64/iterators.md
===================================================================
--- gcc/config/aarch64/iterators.md 2019-08-14 09:29:52.871653684 +0100
+++ gcc/config/aarch64/iterators.md 2019-08-14 09:32:41.846404780 +0100
@@ -480,6 +480,9 @@ (define_c_enum "unspec"
UNSPEC_COND_FCMLT ; Used in aarch64-sve.md.
UNSPEC_COND_FCMNE ; Used in aarch64-sve.md.
UNSPEC_COND_FCMUO ; Used in aarch64-sve.md.
+ UNSPEC_COND_FCVT ; Used in aarch64-sve.md.
+ UNSPEC_COND_FCVTZS ; Used in aarch64-sve.md.
+ UNSPEC_COND_FCVTZU ; Used in aarch64-sve.md.
UNSPEC_COND_FDIV ; Used in aarch64-sve.md.
UNSPEC_COND_FMAXNM ; Used in aarch64-sve.md.
UNSPEC_COND_FMINNM ; Used in aarch64-sve.md.
@@ -498,6 +501,8 @@ (define_c_enum "unspec"
UNSPEC_COND_FRINTZ ; Used in aarch64-sve.md.
UNSPEC_COND_FSQRT ; Used in aarch64-sve.md.
UNSPEC_COND_FSUB ; Used in aarch64-sve.md.
+ UNSPEC_COND_SCVTF ; Used in aarch64-sve.md.
+ UNSPEC_COND_UCVTF ; Used in aarch64-sve.md.
UNSPEC_LASTB ; Used in aarch64-sve.md.
UNSPEC_FCADD90 ; Used in aarch64-simd.md.
UNSPEC_FCADD270 ; Used in aarch64-simd.md.
@@ -1642,6 +1647,9 @@ (define_int_iterator SVE_COND_FP_UNARY [
UNSPEC_COND_FRINTZ
UNSPEC_COND_FSQRT])
+(define_int_iterator SVE_COND_FCVTI [UNSPEC_COND_FCVTZS UNSPEC_COND_FCVTZU])
+(define_int_iterator SVE_COND_ICVTF [UNSPEC_COND_SCVTF UNSPEC_COND_UCVTF])
+
(define_int_iterator SVE_COND_FP_BINARY [UNSPEC_COND_FADD
UNSPEC_COND_FDIV
UNSPEC_COND_FMAXNM
@@ -1715,6 +1723,9 @@ (define_int_attr optab [(UNSPEC_ANDF "an
(UNSPEC_FMINV "smin_nan")
(UNSPEC_COND_FABS "abs")
(UNSPEC_COND_FADD "add")
+ (UNSPEC_COND_FCVT "fcvt")
+ (UNSPEC_COND_FCVTZS "fix_trunc")
+ (UNSPEC_COND_FCVTZU "fixuns_trunc")
(UNSPEC_COND_FDIV "div")
(UNSPEC_COND_FMAXNM "smax")
(UNSPEC_COND_FMINNM "smin")
@@ -1732,7 +1743,9 @@ (define_int_attr optab [(UNSPEC_ANDF "an
(UNSPEC_COND_FRINTX "rint")
(UNSPEC_COND_FRINTZ "btrunc")
(UNSPEC_COND_FSQRT "sqrt")
- (UNSPEC_COND_FSUB "sub")])
+ (UNSPEC_COND_FSUB "sub")
+ (UNSPEC_COND_SCVTF "float")
+ (UNSPEC_COND_UCVTF "floatuns")])
(define_int_attr maxmin_uns [(UNSPEC_UMAXV "umax")
(UNSPEC_UMINV "umin")
@@ -1773,7 +1786,11 @@ (define_int_attr su [(UNSPEC_UNPACKSHI "
(UNSPEC_UNPACKSLO "s")
(UNSPEC_UNPACKULO "u")
(UNSPEC_SMUL_HIGHPART "s")
- (UNSPEC_UMUL_HIGHPART "u")])
+ (UNSPEC_UMUL_HIGHPART "u")
+ (UNSPEC_COND_FCVTZS "s")
+ (UNSPEC_COND_FCVTZU "u")
+ (UNSPEC_COND_SCVTF "s")
+ (UNSPEC_COND_UCVTF "u")])
(define_int_attr sur [(UNSPEC_SHADD "s") (UNSPEC_UHADD "u")
(UNSPEC_SRHADD "sr") (UNSPEC_URHADD "ur")
Index: gcc/config/aarch64/aarch64-sve.md
===================================================================
--- gcc/config/aarch64/aarch64-sve.md 2019-08-14 09:29:52.863653741 +0100
+++ gcc/config/aarch64/aarch64-sve.md 2019-08-14 09:32:41.842404810 +0100
@@ -3643,13 +3643,13 @@ (define_insn "aarch64_sve_<su>unpk<perm_
;; Unpredicated conversion of floats to integers of the same size (HF to HI,
;; SF to SI or DF to DI).
-(define_expand "<fix_trunc_optab><mode><v_int_equiv>2"
+(define_expand "<optab><mode><v_int_equiv>2"
[(set (match_operand:<V_INT_EQUIV> 0 "register_operand")
(unspec:<V_INT_EQUIV>
[(match_dup 2)
- (FIXUORS:<V_INT_EQUIV>
- (match_operand:SVE_F 1 "register_operand"))]
- UNSPEC_MERGE_PTRUE))]
+ (const_int SVE_RELAXED_GP)
+ (match_operand:SVE_F 1 "register_operand")]
+ SVE_COND_FCVTI))]
"TARGET_SVE"
{
operands[2] = aarch64_ptrue_reg (<VPRED>mode);
@@ -3657,37 +3657,37 @@ (define_expand "<fix_trunc_optab><mode><
)
;; Conversion of SF to DI, SI or HI, predicated with a PTRUE.
-(define_insn "*<fix_trunc_optab>v16hsf<mode>2"
+(define_insn "*<optab>v16hsf<mode>2"
[(set (match_operand:SVE_HSDI 0 "register_operand" "=w")
(unspec:SVE_HSDI
[(match_operand:<VPRED> 1 "register_operand" "Upl")
- (FIXUORS:SVE_HSDI
- (match_operand:VNx8HF 2 "register_operand" "w"))]
- UNSPEC_MERGE_PTRUE))]
+ (match_operand:SI 3 "aarch64_sve_gp_strictness")
+ (match_operand:VNx8HF 2 "register_operand" "w")]
+ SVE_COND_FCVTI))]
"TARGET_SVE"
"fcvtz<su>\t%0.<Vetype>, %1/m, %2.h"
)
;; Conversion of SF to DI or SI, predicated with a PTRUE.
-(define_insn "*<fix_trunc_optab>vnx4sf<mode>2"
+(define_insn "*<optab>vnx4sf<mode>2"
[(set (match_operand:SVE_SDI 0 "register_operand" "=w")
(unspec:SVE_SDI
[(match_operand:<VPRED> 1 "register_operand" "Upl")
- (FIXUORS:SVE_SDI
- (match_operand:VNx4SF 2 "register_operand" "w"))]
- UNSPEC_MERGE_PTRUE))]
+ (match_operand:SI 3 "aarch64_sve_gp_strictness")
+ (match_operand:VNx4SF 2 "register_operand" "w")]
+ SVE_COND_FCVTI))]
"TARGET_SVE"
"fcvtz<su>\t%0.<Vetype>, %1/m, %2.s"
)
;; Conversion of DF to DI or SI, predicated with a PTRUE.
-(define_insn "*<fix_trunc_optab>vnx2df<mode>2"
+(define_insn "*<optab>vnx2df<mode>2"
[(set (match_operand:SVE_SDI 0 "register_operand" "=w")
(unspec:SVE_SDI
[(match_operand:VNx2BI 1 "register_operand" "Upl")
- (FIXUORS:SVE_SDI
- (match_operand:VNx2DF 2 "register_operand" "w"))]
- UNSPEC_MERGE_PTRUE))]
+ (match_operand:SI 3 "aarch64_sve_gp_strictness")
+ (match_operand:VNx2DF 2 "register_operand" "w")]
+ SVE_COND_FCVTI))]
"TARGET_SVE"
"fcvtz<su>\t%0.<Vetype>, %1/m, %2.d"
)
@@ -3703,13 +3703,15 @@ (define_expand "vec_pack_<su>fix_trunc_v
[(set (match_dup 4)
(unspec:VNx4SI
[(match_dup 3)
- (FIXUORS:VNx4SI (match_operand:VNx2DF 1 "register_operand"))]
- UNSPEC_MERGE_PTRUE))
+ (const_int SVE_RELAXED_GP)
+ (match_operand:VNx2DF 1 "register_operand")]
+ SVE_COND_FCVTI))
(set (match_dup 5)
(unspec:VNx4SI
[(match_dup 3)
- (FIXUORS:VNx4SI (match_operand:VNx2DF 2 "register_operand"))]
- UNSPEC_MERGE_PTRUE))
+ (const_int SVE_RELAXED_GP)
+ (match_operand:VNx2DF 2 "register_operand")]
+ SVE_COND_FCVTI))
(set (match_operand:VNx4SI 0 "register_operand")
(unspec:VNx4SI [(match_dup 4) (match_dup 5)] UNSPEC_UZP1))]
"TARGET_SVE"
@@ -3740,9 +3742,9 @@ (define_expand "<optab><v_int_equiv><mod
[(set (match_operand:SVE_F 0 "register_operand")
(unspec:SVE_F
[(match_dup 2)
- (FLOATUORS:SVE_F
- (match_operand:<V_INT_EQUIV> 1 "register_operand"))]
- UNSPEC_MERGE_PTRUE))]
+ (const_int SVE_RELAXED_GP)
+ (match_operand:<V_INT_EQUIV> 1 "register_operand")]
+ SVE_COND_ICVTF))]
"TARGET_SVE"
{
operands[2] = aarch64_ptrue_reg (<VPRED>mode);
@@ -3755,11 +3757,11 @@ (define_insn "*<optab><mode>vnx8hf2"
[(set (match_operand:VNx8HF 0 "register_operand" "=w")
(unspec:VNx8HF
[(match_operand:<VPRED> 1 "register_operand" "Upl")
- (FLOATUORS:VNx8HF
- (match_operand:SVE_HSDI 2 "register_operand" "w"))]
- UNSPEC_MERGE_PTRUE))]
+ (match_operand:SI 3 "aarch64_sve_gp_strictness")
+ (match_operand:SVE_HSDI 2 "register_operand" "w")]
+ SVE_COND_ICVTF))]
"TARGET_SVE"
- "<su_optab>cvtf\t%0.h, %1/m, %2.<Vetype>"
+ "<su>cvtf\t%0.h, %1/m, %2.<Vetype>"
)
;; Conversion of DI or SI to the same number of SFs, predicated with a PTRUE.
@@ -3767,11 +3769,11 @@ (define_insn "*<optab><mode>vnx4sf2"
[(set (match_operand:VNx4SF 0 "register_operand" "=w")
(unspec:VNx4SF
[(match_operand:<VPRED> 1 "register_operand" "Upl")
- (FLOATUORS:VNx4SF
- (match_operand:SVE_SDI 2 "register_operand" "w"))]
- UNSPEC_MERGE_PTRUE))]
+ (match_operand:SI 3 "aarch64_sve_gp_strictness")
+ (match_operand:SVE_SDI 2 "register_operand" "w")]
+ SVE_COND_ICVTF))]
"TARGET_SVE"
- "<su_optab>cvtf\t%0.s, %1/m, %2.<Vetype>"
+ "<su>cvtf\t%0.s, %1/m, %2.<Vetype>"
)
;; Conversion of DI or SI to DF, predicated with a PTRUE.
@@ -3779,11 +3781,11 @@ (define_insn "aarch64_sve_<optab><mode>v
[(set (match_operand:VNx2DF 0 "register_operand" "=w")
(unspec:VNx2DF
[(match_operand:VNx2BI 1 "register_operand" "Upl")
- (FLOATUORS:VNx2DF
- (match_operand:SVE_SDI 2 "register_operand" "w"))]
- UNSPEC_MERGE_PTRUE))]
+ (match_operand:SI 3 "aarch64_sve_gp_strictness")
+ (match_operand:SVE_SDI 2 "register_operand" "w")]
+ SVE_COND_ICVTF))]
"TARGET_SVE"
- "<su_optab>cvtf\t%0.d, %1/m, %2.<Vetype>"
+ "<su>cvtf\t%0.d, %1/m, %2.<Vetype>"
)
;; -------------------------------------------------------------------------
@@ -3818,8 +3820,9 @@ (define_expand "vec_unpack<su_optab>_flo
: gen_aarch64_sve_zip1vnx4si)
(temp, operands[1], operands[1]));
rtx ptrue = aarch64_ptrue_reg (VNx2BImode);
- emit_insn (gen_aarch64_sve_<FLOATUORS:optab>vnx4sivnx2df2 (operands[0],
- ptrue, temp));
+ rtx strictness = gen_int_mode (SVE_RELAXED_GP, SImode);
+ emit_insn (gen_aarch64_sve_<FLOATUORS:optab>vnx4sivnx2df2
+ (operands[0], ptrue, temp, strictness));
DONE;
}
)
@@ -3837,15 +3840,15 @@ (define_expand "vec_pack_trunc_<Vwide>"
[(set (match_dup 4)
(unspec:SVE_HSF
[(match_dup 3)
- (unspec:SVE_HSF [(match_operand:<VWIDE> 1 "register_operand")]
- UNSPEC_FLOAT_CONVERT)]
- UNSPEC_MERGE_PTRUE))
+ (const_int SVE_RELAXED_GP)
+ (match_operand:<VWIDE> 1 "register_operand")]
+ UNSPEC_COND_FCVT))
(set (match_dup 5)
(unspec:SVE_HSF
[(match_dup 3)
- (unspec:SVE_HSF [(match_operand:<VWIDE> 2 "register_operand")]
- UNSPEC_FLOAT_CONVERT)]
- UNSPEC_MERGE_PTRUE))
+ (const_int SVE_RELAXED_GP)
+ (match_operand:<VWIDE> 2 "register_operand")]
+ UNSPEC_COND_FCVT))
(set (match_operand:SVE_HSF 0 "register_operand")
(unspec:SVE_HSF [(match_dup 4) (match_dup 5)] UNSPEC_UZP1))]
"TARGET_SVE"
@@ -3862,10 +3865,9 @@ (define_insn "*trunc<Vwide><mode>2"
[(set (match_operand:SVE_HSF 0 "register_operand" "=w")
(unspec:SVE_HSF
[(match_operand:<VWIDE_PRED> 1 "register_operand" "Upl")
- (unspec:SVE_HSF
- [(match_operand:<VWIDE> 2 "register_operand" "w")]
- UNSPEC_FLOAT_CONVERT)]
- UNSPEC_MERGE_PTRUE))]
+ (match_operand:SI 3 "aarch64_sve_gp_strictness")
+ (match_operand:<VWIDE> 2 "register_operand" "w")]
+ UNSPEC_COND_FCVT))]
"TARGET_SVE"
"fcvt\t%0.<Vetype>, %1/m, %2.<Vewtype>"
)
@@ -3896,8 +3898,9 @@ (define_expand "vec_unpacks_<perm_hilo>_
: gen_aarch64_sve_zip1<mode>)
(temp, operands[1], operands[1]));
rtx ptrue = aarch64_ptrue_reg (<VWIDE_PRED>mode);
- emit_insn (gen_aarch64_sve_extend<mode><Vwide>2 (operands[0],
- ptrue, temp));
+ rtx strictness = gen_int_mode (SVE_RELAXED_GP, SImode);
+ emit_insn (gen_aarch64_sve_extend<mode><Vwide>2
+ (operands[0], ptrue, temp, strictness));
DONE;
}
)
@@ -3908,10 +3911,9 @@ (define_insn "aarch64_sve_extend<mode><V
[(set (match_operand:<VWIDE> 0 "register_operand" "=w")
(unspec:<VWIDE>
[(match_operand:<VWIDE_PRED> 1 "register_operand" "Upl")
- (unspec:<VWIDE>
- [(match_operand:SVE_HSF 2 "register_operand" "w")]
- UNSPEC_FLOAT_CONVERT)]
- UNSPEC_MERGE_PTRUE))]
+ (match_operand:SI 3 "aarch64_sve_gp_strictness")
+ (match_operand:SVE_HSF 2 "register_operand" "w")]
+ UNSPEC_COND_FCVT))]
"TARGET_SVE"
"fcvt\t%0.<Vewtype>, %1/m, %2.<Vetype>"
)
