2019-08-05 Arvind Sankar <[email protected]>
gcc/ChangeLog:
* common.md: Convert GET_CODE (..) == CONST_VECTOR to
CONST_VECTOR_P (..).
* config/aarch64/aarch64.c: Likewise.
* config/alpha/alpha.c: Likewise.
* config/arc/arc.c: Likewise.
* config/arc/simdext.md: Likewise.
* config/arm/arm.c: Likewise.
* config/bfin/bfin.md: Likewise.
* config/darwin.c: Likewise.
* config/gcn/gcn-valu.md: Likewise.
* config/gcn/gcn.c: Likewise.
* config/i386/i386-expand.c: Likewise.
* config/i386/i386.c: Likewise.
* config/i386/predicates.md: Likewise.
* config/i386/sse.md: Likewise.
* config/ia64/ia64.c: Likewise.
* config/mips/mips.c: Likewise.
* config/nds32/nds32-dspext.md: Likewise.
* config/nds32/predicates.md: Likewise.
* config/rs6000/predicates.md: Likewise.
* config/rs6000/rs6000-p8swap.c: Likewise.
* config/rs6000/rs6000.c: Likewise.
* config/s390/s390.c: Likewise.
* config/spu/predicates.md: Likewise.
* config/spu/spu.c: Likewise.
* config/tilegx/tilegx.c: Likewise.
* config/tilepro/tilepro.c: Likewise.
* dwarf2out.c: Likewise.
* emit-rtl.c: Likewise.
* explow.c: Likewise.
* rtlanal.c: Likewise.
* simplify-rtx.c: Likewise.
* varasm.c: Likewise.
32 files changed, 112 insertions(+), 112 deletions(-)
diff --git a/gcc/common.md b/gcc/common.md
index 42c574029b5..ee93f203bd2 100644
--- a/gcc/common.md
+++ b/gcc/common.md
@@ -80,14 +80,14 @@
(define_constraint "E"
"Matches a floating-point constant."
(ior (match_test "CONST_DOUBLE_AS_FLOAT_P (op)")
- (match_test "GET_CODE (op) == CONST_VECTOR
+ (match_test "CONST_VECTOR_P (op)
&& GET_MODE_CLASS (GET_MODE (op)) == MODE_VECTOR_FLOAT")))
;; There is no longer a distinction between "E" and "F".
(define_constraint "F"
"Matches a floating-point constant."
(ior (match_test "CONST_DOUBLE_AS_FLOAT_P (op)")
- (match_test "GET_CODE (op) == CONST_VECTOR
+ (match_test "CONST_VECTOR_P (op)
&& GET_MODE_CLASS (GET_MODE (op)) == MODE_VECTOR_FLOAT")))
(define_constraint "X"
diff --git a/gcc/config/aarch64/aarch64.c b/gcc/config/aarch64/aarch64.c
index 68ad4858c76..9bdbc198dae 100644
--- a/gcc/config/aarch64/aarch64.c
+++ b/gcc/config/aarch64/aarch64.c
@@ -3429,7 +3429,7 @@ aarch64_expand_mov_immediate (rtx dest, rtx imm,
}
emit_insn (gen_vec_duplicate (dest, op));
}
- else if (GET_CODE (imm) == CONST_VECTOR
+ else if (CONST_VECTOR_P (imm)
&& !GET_MODE_NUNITS (GET_MODE (imm)).is_constant ())
aarch64_expand_sve_const_vector (dest, imm);
else
@@ -7503,7 +7503,7 @@ aarch64_const_vec_all_in_range_p (rtx vec,
HOST_WIDE_INT minval,
HOST_WIDE_INT maxval)
{
- if (GET_CODE (vec) != CONST_VECTOR
+ if (!CONST_VECTOR_P (vec)
|| GET_MODE_CLASS (GET_MODE (vec)) != MODE_VECTOR_INT)
return false;
@@ -13203,7 +13203,7 @@ aarch64_legitimate_constant_p (machine_mode mode, rtx x)
/* Support CSE and rematerialization of common constants. */
if (CONST_INT_P (x)
|| (CONST_DOUBLE_P (x) && GET_MODE_CLASS (mode) == MODE_FLOAT)
- || GET_CODE (x) == CONST_VECTOR)
+ || CONST_VECTOR_P (x))
return true;
/* Do not allow vector struct mode constants for Advanced SIMD.
@@ -14621,7 +14621,7 @@ aarch64_simd_valid_immediate (rtx op,
simd_immediate_info *info,
scalar_mode elt_mode = GET_MODE_INNER (mode);
rtx base, step;
unsigned int n_elts;
- if (GET_CODE (op) == CONST_VECTOR
+ if (CONST_VECTOR_P (op)
&& CONST_VECTOR_DUPLICATE_P (op))
n_elts = CONST_VECTOR_NPATTERNS (op);
else if ((vec_flags & VEC_SVE_DATA)
@@ -14636,7 +14636,7 @@ aarch64_simd_valid_immediate (rtx op,
simd_immediate_info *info,
*info = simd_immediate_info (elt_mode, base, step);
return true;
}
- else if (GET_CODE (op) == CONST_VECTOR
+ else if (CONST_VECTOR_P (op)
&& CONST_VECTOR_NUNITS (op).is_constant (&n_elts))
/* N_ELTS set above. */;
else
@@ -15096,7 +15096,7 @@ aarch64_simd_make_constant (rtx vals)
int n_const = 0;
int i;
- if (GET_CODE (vals) == CONST_VECTOR)
+ if (CONST_VECTOR_P (vals))
const_vec = vals;
else if (GET_CODE (vals) == PARALLEL)
{
@@ -16548,7 +16548,7 @@ aarch64_expand_sve_vec_perm (rtx target, rtx op0, rtx
op1, rtx sel)
rtx sel_reg = force_reg (sel_mode, sel);
/* Check if the sel only references the first values vector. */
- if (GET_CODE (sel) == CONST_VECTOR
+ if (CONST_VECTOR_P (sel)
&& aarch64_const_vec_all_in_range_p (sel, 0, nunits - 1))
{
emit_unspec2 (target, UNSPEC_TBL, op0, sel_reg);
@@ -16570,7 +16570,7 @@ aarch64_expand_sve_vec_perm (rtx target, rtx op0, rtx
op1, rtx sel)
rtx res0 = gen_reg_rtx (data_mode);
rtx res1 = gen_reg_rtx (data_mode);
rtx neg_num_elems = aarch64_simd_gen_const_vector_dup (sel_mode, -nunits);
- if (GET_CODE (sel) != CONST_VECTOR
+ if (!CONST_VECTOR_P (sel)
|| !aarch64_const_vec_all_in_range_p (sel, 0, 2 * nunits - 1))
{
rtx max_sel = aarch64_simd_gen_const_vector_dup (sel_mode,
@@ -18754,7 +18754,7 @@ int
aarch64_vec_fpconst_pow_of_2 (rtx x)
{
int nelts;
- if (GET_CODE (x) != CONST_VECTOR
+ if (!CONST_VECTOR_P (x)
|| !CONST_VECTOR_NUNITS (x).is_constant (&nelts))
return -1;
diff --git a/gcc/config/alpha/alpha.c b/gcc/config/alpha/alpha.c
index 132af0b592a..f0e4061fb00 100644
--- a/gcc/config/alpha/alpha.c
+++ b/gcc/config/alpha/alpha.c
@@ -1623,7 +1623,7 @@ alpha_preferred_reload_class(rtx x, enum reg_class rclass)
/* These sorts of constants we can easily drop to memory. */
if (CONST_SCALAR_INT_P (x)
|| CONST_DOUBLE_P (x)
- || GET_CODE (x) == CONST_VECTOR)
+ || CONST_VECTOR_P (x))
{
if (rclass == FLOAT_REGS)
return NO_REGS;
@@ -2112,7 +2112,7 @@ alpha_emit_set_long_const (rtx target, HOST_WIDE_INT c1)
static HOST_WIDE_INT
alpha_extract_integer (rtx x)
{
- if (GET_CODE (x) == CONST_VECTOR)
+ if (CONST_VECTOR_P (x))
x = simplify_subreg (DImode, x, GET_MODE (x), 0);
gcc_assert (CONST_INT_P (x));
@@ -2248,7 +2248,7 @@ alpha_expand_mov (machine_mode mode, rtx *operands)
/* Split large integers. */
if (CONST_INT_P (operands[1])
- || GET_CODE (operands[1]) == CONST_VECTOR)
+ || CONST_VECTOR_P (operands[1]))
{
if (alpha_split_const_mov (mode, operands))
return true;
diff --git a/gcc/config/arc/arc.c b/gcc/config/arc/arc.c
index abdb51fbb31..d9225440c3f 100644
--- a/gcc/config/arc/arc.c
+++ b/gcc/config/arc/arc.c
@@ -10105,7 +10105,7 @@ arc_split_move (rtx *operands)
}
if (TARGET_PLUS_QMACW
- && GET_CODE (operands[1]) == CONST_VECTOR)
+ && CONST_VECTOR_P (operands[1]))
{
HOST_WIDE_INT intval0, intval1;
if (GET_MODE (operands[1]) == V2SImode)
diff --git a/gcc/config/arc/simdext.md b/gcc/config/arc/simdext.md
index 9e4b9ba2628..53a0a90ef3b 100644
--- a/gcc/config/arc/simdext.md
+++ b/gcc/config/arc/simdext.md
@@ -1365,7 +1365,7 @@
mov%? %0, %1
ld%U1%V1 %0,%1
st%U0%V0 %1,%0"
- "reload_completed && GET_CODE (operands[1]) == CONST_VECTOR"
+ "reload_completed && CONST_VECTOR_P (operands[1])"
[(set (match_dup 0) (match_dup 2))]
{
HOST_WIDE_INT intval = INTVAL (XVECEXP (operands[1], 0, 1)) << 16;
diff --git a/gcc/config/arm/arm.c b/gcc/config/arm/arm.c
index 81286cadf32..a6b493f2973 100644
--- a/gcc/config/arm/arm.c
+++ b/gcc/config/arm/arm.c
@@ -12002,7 +12002,7 @@ neon_valid_immediate (rtx op, machine_mode mode, int
inverse,
unsigned char bytes[16];
int immtype = -1, matches;
unsigned int invmask = inverse ? 0xff : 0;
- bool vector = GET_CODE (op) == CONST_VECTOR;
+ bool vector = CONST_VECTOR_P (op);
if (vector)
n_elts = CONST_VECTOR_NUNITS (op);
@@ -12352,7 +12352,7 @@ neon_vdup_constant (rtx vals)
machine_mode inner_mode = GET_MODE_INNER (mode);
rtx x;
- if (GET_CODE (vals) != CONST_VECTOR || GET_MODE_SIZE (inner_mode) > 4)
+ if (!CONST_VECTOR_P (vals) || GET_MODE_SIZE (inner_mode) > 4)
return NULL_RTX;
if (!const_vec_duplicate_p (vals, &x))
@@ -12385,7 +12385,7 @@ neon_make_constant (rtx vals)
int n_const = 0;
int i;
- if (GET_CODE (vals) == CONST_VECTOR)
+ if (CONST_VECTOR_P (vals))
const_vec = vals;
else if (GET_CODE (vals) == PARALLEL)
{
@@ -12793,7 +12793,7 @@ coproc_secondary_reload_class (machine_mode mode, rtx
x, bool wb)
/* The neon move patterns handle all legitimate vector and struct
addresses. */
if (TARGET_NEON
- && (MEM_P (x) || GET_CODE (x) == CONST_VECTOR)
+ && (MEM_P (x) || CONST_VECTOR_P (x))
&& (GET_MODE_CLASS (mode) == MODE_VECTOR_INT
|| GET_MODE_CLASS (mode) == MODE_VECTOR_FLOAT
|| VALID_NEON_STRUCT_MODE (mode)))
@@ -23060,7 +23060,7 @@ arm_assemble_integer (rtx x, unsigned int size, int
aligned_p)
{
int i, units;
- gcc_assert (GET_CODE (x) == CONST_VECTOR);
+ gcc_assert (CONST_VECTOR_P (x));
units = CONST_VECTOR_NUNITS (x);
size = GET_MODE_UNIT_SIZE (mode);
@@ -26982,7 +26982,7 @@ arm_emit_vector_const (FILE *file, rtx x)
int i;
const char * pattern;
- gcc_assert (GET_CODE (x) == CONST_VECTOR);
+ gcc_assert (CONST_VECTOR_P (x));
switch (GET_MODE (x))
{
@@ -28000,7 +28000,7 @@ arm_output_addr_const_extra (FILE *fp, rtx x)
fputc (')', fp);
return TRUE;
}
- else if (GET_CODE (x) == CONST_VECTOR)
+ else if (CONST_VECTOR_P (x))
return arm_emit_vector_const (fp, x);
return FALSE;
diff --git a/gcc/config/bfin/bfin.md b/gcc/config/bfin/bfin.md
index b2b5f04d6c5..517ee4baa39 100644
--- a/gcc/config/bfin/bfin.md
+++ b/gcc/config/bfin/bfin.md
@@ -653,7 +653,7 @@
%0 = %1;
%0 = %1%!
%0 = %1%!"
- "reload_completed && GET_CODE (operands[1]) == CONST_VECTOR"
+ "reload_completed && CONST_VECTOR_P (operands[1])"
[(set (match_dup 0) (high:SI (match_dup 2)))
(set (match_dup 0) (lo_sum:SI (match_dup 0) (match_dup 3)))]
{
diff --git a/gcc/config/darwin.c b/gcc/config/darwin.c
index 3076650abaa..8ccbad46310 100644
--- a/gcc/config/darwin.c
+++ b/gcc/config/darwin.c
@@ -1765,7 +1765,7 @@ machopic_select_rtx_section (machine_mode mode, rtx x,
&& (CONST_INT_P (x)
|| CONST_WIDE_INT_P (x)
|| CONST_DOUBLE_P (x)
- || GET_CODE (x) == CONST_VECTOR))
+ || CONST_VECTOR_P (x)))
return darwin_sections[literal16_section];
else if (MACHOPIC_INDIRECT
&& (GET_CODE (x) == SYMBOL_REF
diff --git a/gcc/config/gcn/gcn-valu.md b/gcc/config/gcn/gcn-valu.md
index df0fe33878b..e6a95bf6fb4 100644
--- a/gcc/config/gcn/gcn-valu.md
+++ b/gcc/config/gcn/gcn-valu.md
@@ -2322,7 +2322,7 @@
rtx fma = gen_reg_rtx (<MODE>mode);
rtx rcp;
- bool is_rcp = (GET_CODE (operands[1]) == CONST_VECTOR
+ bool is_rcp = (CONST_VECTOR_P (operands[1])
&& real_identical
(CONST_DOUBLE_REAL_VALUE
(CONST_VECTOR_ELT (operands[1], 0)), &dconstm1));
diff --git a/gcc/config/gcn/gcn.c b/gcc/config/gcn/gcn.c
index 8bc1e6b50be..b4c5f228373 100644
--- a/gcc/config/gcn/gcn.c
+++ b/gcc/config/gcn/gcn.c
@@ -561,7 +561,7 @@ gcn_operand_part (machine_mode mode, rtx op, int n)
gcc_assert (REGNO (op) + n < FIRST_PSEUDO_REGISTER);
return gen_rtx_REG (V64SImode, REGNO (op) + n);
}
- if (GET_CODE (op) == CONST_VECTOR)
+ if (CONST_VECTOR_P (op))
{
int units = GET_MODE_NUNITS (mode);
rtvec v = rtvec_alloc (units);
@@ -734,7 +734,7 @@ gcn_inline_fp_constant_p (rtx x, bool allow_vector)
&& allow_vector)
{
int n;
- if (GET_CODE (x) != CONST_VECTOR)
+ if (!CONST_VECTOR_P (x))
return 0;
n = gcn_inline_fp_constant_p (CONST_VECTOR_ELT (x, 0), false);
if (!n)
@@ -799,7 +799,7 @@ gcn_fp_constant_p (rtx x, bool allow_vector)
&& allow_vector)
{
int n;
- if (GET_CODE (x) != CONST_VECTOR)
+ if (!CONST_VECTOR_P (x))
return false;
n = gcn_fp_constant_p (CONST_VECTOR_ELT (x, 0), false);
if (!n)
@@ -828,7 +828,7 @@ gcn_inline_constant_p (rtx x)
return INTVAL (x) >= -16 && INTVAL (x) < 64;
if (CONST_DOUBLE_P (x))
return gcn_inline_fp_constant_p (x, false);
- if (GET_CODE (x) == CONST_VECTOR)
+ if (CONST_VECTOR_P (x))
{
int n;
if (!vgpr_vector_mode_p (GET_MODE (x)))
@@ -890,7 +890,7 @@ gcn_constant_p (rtx x)
bool
gcn_inline_constant64_p (rtx x)
{
- if (GET_CODE (x) == CONST_VECTOR)
+ if (CONST_VECTOR_P (x))
{
if (!vgpr_vector_mode_p (GET_MODE (x)))
return false;
@@ -950,7 +950,7 @@ gcn_legitimate_constant_p (machine_mode, rtx x)
static bool
single_cst_vector_p (rtx x)
{
- if (GET_CODE (x) != CONST_VECTOR)
+ if (!CONST_VECTOR_P (x))
return false;
for (int i = 1; i < 64; i++)
if (CONST_VECTOR_ELT (x, i) != CONST_VECTOR_ELT (x, 0))
@@ -1352,7 +1352,7 @@ gcn_addr_space_legitimate_address_p (machine_mode mode,
rtx x, bool strict,
&& !gcn_ssrc_register_operand (x1, DImode)))
return false;
}
- else if (GET_CODE (x1) == CONST_VECTOR
+ else if (CONST_VECTOR_P (x1)
&& CONST_INT_P (CONST_VECTOR_ELT (x1, 0))
&& single_cst_vector_p (x1))
{
@@ -5676,7 +5676,7 @@ print_operand (FILE *file, rtx x, int code)
return;
}
rtx val = XEXP (x0, 1);
- if (GET_CODE (val) == CONST_VECTOR)
+ if (CONST_VECTOR_P (val))
val = CONST_VECTOR_ELT (val, 0);
if (!CONST_INT_P (val))
{
diff --git a/gcc/config/i386/i386-expand.c b/gcc/config/i386/i386-expand.c
index f6e6d68eed2..0741c47bdb6 100644
--- a/gcc/config/i386/i386-expand.c
+++ b/gcc/config/i386/i386-expand.c
@@ -963,11 +963,11 @@ ix86_expand_vector_logical_operator (enum rtx_code code,
machine_mode mode,
to cast them temporarily to integer vectors. */
if (op1
&& !TARGET_SSE_PACKED_SINGLE_INSN_OPTIMAL
- && (SUBREG_P (op2) || GET_CODE (op2) == CONST_VECTOR)
+ && (SUBREG_P (op2) || CONST_VECTOR_P (op2))
&& GET_MODE_CLASS (GET_MODE (SUBREG_REG (op1))) == MODE_VECTOR_FLOAT
&& GET_MODE_SIZE (GET_MODE (SUBREG_REG (op1))) == GET_MODE_SIZE (mode)
&& SUBREG_BYTE (op1) == 0
- && (GET_CODE (op2) == CONST_VECTOR
+ && (CONST_VECTOR_P (op2)
|| (GET_MODE (SUBREG_REG (op1)) == GET_MODE (SUBREG_REG (op2))
&& SUBREG_BYTE (op2) == 0))
&& can_create_pseudo_p ())
@@ -982,7 +982,7 @@ ix86_expand_vector_logical_operator (enum rtx_code code,
machine_mode mode,
case E_V4DFmode:
case E_V8DFmode:
dst = gen_reg_rtx (GET_MODE (SUBREG_REG (op1)));
- if (GET_CODE (op2) == CONST_VECTOR)
+ if (CONST_VECTOR_P (op2))
{
op2 = gen_lowpart (GET_MODE (dst), op2);
op2 = force_reg (GET_MODE (dst), op2);
@@ -5128,7 +5128,7 @@ ix86_split_to_parts (rtx operand, rtx *parts,
machine_mode mode)
return size;
}
- if (GET_CODE (operand) == CONST_VECTOR)
+ if (CONST_VECTOR_P (operand))
{
scalar_int_mode imode = int_mode_for_mode (mode).require ();
/* Caution: if we looked through a constant pool memory above,
@@ -19504,7 +19504,7 @@ const_vector_equal_evenodd_p (rtx op)
{
machine_mode mode = GET_MODE (op);
int i, nunits = GET_MODE_NUNITS (mode);
- if (GET_CODE (op) != CONST_VECTOR
+ if (!CONST_VECTOR_P (op)
|| nunits != CONST_VECTOR_NUNITS (op))
return false;
for (i = 0; i < nunits; i += 2)
diff --git a/gcc/config/i386/i386.c b/gcc/config/i386/i386.c
index e278d9c76df..180a0a1c88d 100644
--- a/gcc/config/i386/i386.c
+++ b/gcc/config/i386/i386.c
@@ -12942,7 +12942,7 @@ ix86_print_operand (FILE *file, rtx x, int code)
/* We have patterns that allow zero sets of memory, for instance.
In 64-bit mode, we should probably support all 8-byte vectors,
since we can in fact encode that into an immediate. */
- if (GET_CODE (x) == CONST_VECTOR)
+ if (CONST_VECTOR_P (x))
{
if (x != CONST0_RTX (GET_MODE (x)))
output_operand_lossage ("invalid vector immediate");
diff --git a/gcc/config/i386/predicates.md b/gcc/config/i386/predicates.md
index 5e8f6710137..d36ded363c2 100644
--- a/gcc/config/i386/predicates.md
+++ b/gcc/config/i386/predicates.md
@@ -1017,7 +1017,7 @@
unsigned n_elts;
op = avoid_constant_pool_reference (op);
- if (GET_CODE (op) != CONST_VECTOR)
+ if (!CONST_VECTOR_P (op))
return false;
n_elts = CONST_VECTOR_NUNITS (op);
diff --git a/gcc/config/i386/sse.md b/gcc/config/i386/sse.md
index 3391724fd8d..a8a529ec18e 100644
--- a/gcc/config/i386/sse.md
+++ b/gcc/config/i386/sse.md
@@ -8634,7 +8634,7 @@
lo insns have =m and 0C constraints. */
: (operands[2] != const0_rtx
|| (!rtx_equal_p (dest, operands[3])
- && GET_CODE (operands[3]) != CONST_VECTOR))))
+ && !CONST_VECTOR_P (operands[3])))))
dest = gen_reg_rtx (<ssehalfvecmode>mode);
switch (INTVAL (operands[2]))
{
diff --git a/gcc/config/ia64/ia64.c b/gcc/config/ia64/ia64.c
index e1206e2b10e..6896b299ba1 100644
--- a/gcc/config/ia64/ia64.c
+++ b/gcc/config/ia64/ia64.c
@@ -5581,7 +5581,7 @@ ia64_print_operand (FILE * file, rtx x, int code)
return;
case 'v':
- gcc_assert (GET_CODE (x) == CONST_VECTOR);
+ gcc_assert (CONST_VECTOR_P (x));
x = simplify_subreg (DImode, x, GET_MODE (x), 0);
break;
diff --git a/gcc/config/mips/mips.c b/gcc/config/mips/mips.c
index 7f14a077d8d..96dff88c77d 100644
--- a/gcc/config/mips/mips.c
+++ b/gcc/config/mips/mips.c
@@ -1880,7 +1880,7 @@ mips_symbol_binds_local_p (const_rtx x)
bool
mips_const_vector_bitimm_set_p (rtx op, machine_mode mode)
{
- if (GET_CODE (op) == CONST_VECTOR && op != CONST0_RTX (mode))
+ if (CONST_VECTOR_P (op) && op != CONST0_RTX (mode))
{
unsigned HOST_WIDE_INT val = UINTVAL (CONST_VECTOR_ELT (op, 0));
int vlog2 = exact_log2 (val & GET_MODE_MASK (GET_MODE_INNER (mode)));
@@ -1902,7 +1902,7 @@ mips_const_vector_bitimm_set_p (rtx op, machine_mode mode)
bool
mips_const_vector_bitimm_clr_p (rtx op, machine_mode mode)
{
- if (GET_CODE (op) == CONST_VECTOR && op != CONSTM1_RTX (mode))
+ if (CONST_VECTOR_P (op) && op != CONSTM1_RTX (mode))
{
unsigned HOST_WIDE_INT val = ~UINTVAL (CONST_VECTOR_ELT (op, 0));
int vlog2 = exact_log2 (val & GET_MODE_MASK (GET_MODE_INNER (mode)));
@@ -1927,7 +1927,7 @@ mips_const_vector_same_val_p (rtx op, machine_mode mode)
int i, nunits = GET_MODE_NUNITS (mode);
rtx first;
- if (GET_CODE (op) != CONST_VECTOR || GET_MODE (op) != mode)
+ if (!CONST_VECTOR_P (op) || GET_MODE (op) != mode)
return false;
first = CONST_VECTOR_ELT (op, 0);
@@ -9026,7 +9026,7 @@ mips_print_operand (FILE *file, rtx op, int letter)
switch (letter)
{
case 'E':
- if (GET_CODE (op) == CONST_VECTOR)
+ if (CONST_VECTOR_P (op))
{
gcc_assert (mips_const_vector_same_val_p (op, GET_MODE (op)));
op = CONST_VECTOR_ELT (op, 0);
@@ -9059,7 +9059,7 @@ mips_print_operand (FILE *file, rtx op, int letter)
break;
case 'B':
- if (GET_CODE (op) == CONST_VECTOR)
+ if (CONST_VECTOR_P (op))
{
gcc_assert (mips_const_vector_same_val_p (op, GET_MODE (op)));
op = CONST_VECTOR_ELT (op, 0);
@@ -9092,7 +9092,7 @@ mips_print_operand (FILE *file, rtx op, int letter)
break;
case 'V':
- if (GET_CODE (op) == CONST_VECTOR)
+ if (CONST_VECTOR_P (op))
{
machine_mode mode = GET_MODE_INNER (GET_MODE (op));
unsigned HOST_WIDE_INT val = UINTVAL (CONST_VECTOR_ELT (op, 0));
diff --git a/gcc/config/nds32/nds32-dspext.md b/gcc/config/nds32/nds32-dspext.md
index 116cb7f599a..578c623504b 100644
--- a/gcc/config/nds32/nds32-dspext.md
+++ b/gcc/config/nds32/nds32-dspext.md
@@ -29,7 +29,7 @@
/* If operands[1] is a large constant and cannot be performed
by a single instruction, we need to split it. */
- if (GET_CODE (operands[1]) == CONST_VECTOR
+ if (CONST_VECTOR_P (operands[1])
&& !satisfies_constraint_CVs2 (operands[1])
&& !satisfies_constraint_CVhi (operands[1]))
{
diff --git a/gcc/config/nds32/predicates.md b/gcc/config/nds32/predicates.md
index 79ae8ea2a34..9983eb4c409 100644
--- a/gcc/config/nds32/predicates.md
+++ b/gcc/config/nds32/predicates.md
@@ -129,7 +129,7 @@
{
/* If the constant op does NOT satisfy Is20 nor Ihig,
we cannot perform move behavior by a single instruction. */
- if (GET_CODE (op) == CONST_VECTOR
+ if (CONST_VECTOR_P (op)
&& !satisfies_constraint_CVs2 (op)
&& !satisfies_constraint_CVhi (op))
return false;
diff --git a/gcc/config/rs6000/predicates.md b/gcc/config/rs6000/predicates.md
index 4e77063249a..62bf292b42b 100644
--- a/gcc/config/rs6000/predicates.md
+++ b/gcc/config/rs6000/predicates.md
@@ -1045,7 +1045,7 @@
return 1;
/* Allow easy vector constants. */
- if (GET_CODE (op) == CONST_VECTOR
+ if (CONST_VECTOR_P (op)
&& easy_vector_constant (op, mode))
return 1;
diff --git a/gcc/config/rs6000/rs6000-p8swap.c
b/gcc/config/rs6000/rs6000-p8swap.c
index c3b98315503..ffe5d9a925f 100644
--- a/gcc/config/rs6000/rs6000-p8swap.c
+++ b/gcc/config/rs6000/rs6000-p8swap.c
@@ -595,7 +595,7 @@ const_load_sequence_p (swap_web_entry *insn_entry, rtx insn)
if (SYMBOL_REF_P (const_vector)
&& CONSTANT_POOL_ADDRESS_P (const_vector))
const_vector = get_pool_constant (const_vector);
- if (GET_CODE (const_vector) != CONST_VECTOR)
+ if (!CONST_VECTOR_P (const_vector))
return false;
}
}
@@ -1116,7 +1116,7 @@ swap_const_vector_halves (rtx *op_ptr)
int i;
rtx op = *op_ptr;
enum rtx_code code = GET_CODE (op);
- if (GET_CODE (op) == CONST_VECTOR)
+ if (CONST_VECTOR_P (op))
{
int units = GET_MODE_NUNITS (GET_MODE (op));
rtx_vector_builder builder (GET_MODE (op), units, 1);
@@ -1371,7 +1371,7 @@ adjust_vperm (rtx_insn *insn)
constant. */
if (SYMBOL_REF_P (const_vector))
const_vector = get_pool_constant (const_vector);
- gcc_assert (GET_CODE (const_vector) == CONST_VECTOR);
+ gcc_assert (CONST_VECTOR_P (const_vector));
/* Create an adjusted mask from the initial mask. */
unsigned int new_mask[16], i, val;
@@ -1851,7 +1851,7 @@ replace_swapped_load_constant (swap_web_entry
*insn_entry, rtx swap_insn)
constant. */
if (SYMBOL_REF_P (const_vector))
const_vector = get_pool_constant (const_vector);
- gcc_assert (GET_CODE (const_vector) == CONST_VECTOR);
+ gcc_assert (CONST_VECTOR_P (const_vector));
rtx new_mem;
enum machine_mode mode = GET_MODE (const_vector);
diff --git a/gcc/config/rs6000/rs6000.c b/gcc/config/rs6000/rs6000.c
index 1650adda137..d84e743c1af 100644
--- a/gcc/config/rs6000/rs6000.c
+++ b/gcc/config/rs6000/rs6000.c
@@ -6004,7 +6004,7 @@ xxspltib_constant_p (rtx op,
}
/* Handle (const_vector [...]). */
- else if (GET_CODE (op) == CONST_VECTOR)
+ else if (CONST_VECTOR_P (op))
{
if (mode != V16QImode && mode != V8HImode && mode != V4SImode
&& mode != V2DImode)
@@ -11814,7 +11814,7 @@ rs6000_preferred_reload_class (rtx x, enum reg_class
rclass)
/* If this is a vector constant that can be formed with a few Altivec
instructions, we want altivec registers. */
- if (GET_CODE (x) == CONST_VECTOR && easy_vector_constant (x, mode))
+ if (CONST_VECTOR_P (x) && easy_vector_constant (x, mode))
return ALTIVEC_REGS;
/* If this is an integer constant that can easily be loaded into
@@ -12316,7 +12316,7 @@ rs6000_output_move_128bit (rtx operands[])
&& (CONST_INT_P (src)
|| CONST_WIDE_INT_P (src)
|| CONST_DOUBLE_P (src)
- || GET_CODE (src) == CONST_VECTOR))
+ || CONST_VECTOR_P (src)))
{
if (dest_gpr_p)
return "#";
@@ -14646,8 +14646,8 @@ rs6000_emit_vector_cond_expr (rtx dest, rtx op_true,
rtx op_false,
/* Optimize vec1 == vec2, to know the mask generates -1/0. */
if (GET_MODE_CLASS (dest_mode) == MODE_VECTOR_INT
- && (GET_CODE (op_true) == CONST_VECTOR
- || GET_CODE (op_false) == CONST_VECTOR))
+ && (CONST_VECTOR_P (op_true)
+ || CONST_VECTOR_P (op_false)))
{
rtx constant_0 = CONST0_RTX (dest_mode);
rtx constant_m1 = CONSTM1_RTX (dest_mode);
@@ -24116,7 +24116,7 @@ rs6000_legitimate_constant_p (machine_mode mode, rtx x)
if (CONST_DOUBLE_P (x))
return easy_fp_constant (x, mode);
- if (GET_CODE (x) == CONST_VECTOR)
+ if (CONST_VECTOR_P (x))
return easy_vector_constant (x, mode);
return true;
diff --git a/gcc/config/s390/s390.c b/gcc/config/s390/s390.c
index ff6d41ea6f0..31fc179645d 100644
--- a/gcc/config/s390/s390.c
+++ b/gcc/config/s390/s390.c
@@ -2494,7 +2494,7 @@ s390_bytemask_vector_p (rtx op, unsigned *mask)
int nunit, unit_size;
if (!VECTOR_MODE_P (GET_MODE (op))
- || GET_CODE (op) != CONST_VECTOR
+ || !CONST_VECTOR_P (op)
|| !CONST_INT_P (XVECEXP (op, 0, 0)))
return false;
@@ -4040,7 +4040,7 @@ legitimate_pic_operand_p (rtx op)
static bool
s390_legitimate_constant_p (machine_mode mode, rtx op)
{
- if (TARGET_VX && VECTOR_MODE_P (mode) && GET_CODE (op) == CONST_VECTOR)
+ if (TARGET_VX && VECTOR_MODE_P (mode) && CONST_VECTOR_P (op))
{
if (GET_MODE_SIZE (mode) != 16)
return 0;
@@ -4419,7 +4419,7 @@ s390_reload_symref_address (rtx reg, rtx mem, rtx
scratch, bool tomem)
Force it back in. */
if (CONST_INT_P (mem) || CONST_DOUBLE_P (mem)
|| CONST_WIDE_INT_P (mem)
- || GET_CODE (mem) == CONST_VECTOR
+ || CONST_VECTOR_P (mem)
|| GET_CODE (mem) == CONST)
mem = force_const_mem (GET_MODE (reg), mem);
@@ -9285,7 +9285,7 @@ s390_output_pool_entry (rtx exp, machine_mode mode,
unsigned int align)
{
int i;
machine_mode inner_mode;
- gcc_assert (GET_CODE (exp) == CONST_VECTOR);
+ gcc_assert (CONST_VECTOR_P (exp));
inner_mode = GET_MODE_INNER (GET_MODE (exp));
for (i = 0; i < XVECLEN (exp, 0); i++)
diff --git a/gcc/config/spu/predicates.md b/gcc/config/spu/predicates.md
index 6a2b38eadef..2b51d015cf3 100644
--- a/gcc/config/spu/predicates.md
+++ b/gcc/config/spu/predicates.md
@@ -65,7 +65,7 @@
{
if (spu_reg_operand (op, mode))
return 1;
- if (CONST_INT_P (op) || GET_CODE (op) == CONST_VECTOR)
+ if (CONST_INT_P (op) || CONST_VECTOR_P (op))
return arith_immediate_p (op, mode, -0x200, 0x1ff);
return 0;
})
@@ -76,7 +76,7 @@
if (spu_reg_operand (op, mode))
return 1;
if (CONST_INT_P (op) || CONST_DOUBLE_P (op)
- || GET_CODE (op) == CONST_VECTOR)
+ || CONST_VECTOR_P (op))
return logical_immediate_p (op, mode);
return 0;
})
@@ -87,7 +87,7 @@
if (spu_reg_operand (op, mode))
return 1;
if (CONST_INT_P (op) || CONST_DOUBLE_P (op)
- || GET_CODE (op) == CONST_VECTOR)
+ || CONST_VECTOR_P (op))
return logical_immediate_p (op, mode)
|| iohl_immediate_p (op, mode);
return 0;
diff --git a/gcc/config/spu/spu.c b/gcc/config/spu/spu.c
index b2ca39a6fb0..fe893b62a9e 100644
--- a/gcc/config/spu/spu.c
+++ b/gcc/config/spu/spu.c
@@ -1277,7 +1277,7 @@ print_operand (FILE * file, rtx x, int code)
case IC_IL1s:
if (xcode == HIGH)
x = XEXP (x, 0);
- if (GET_CODE (x) == CONST_VECTOR)
+ if (CONST_VECTOR_P (x))
x = CONST_VECTOR_ELT (x, 0);
output_addr_const (file, x);
if (xcode == HIGH)
@@ -3173,7 +3173,7 @@ classify_immediate (rtx op, machine_mode mode)
/* A V4SI const_vector with all identical symbols is ok. */
if (!flag_pic
&& mode == V4SImode
- && GET_CODE (op) == CONST_VECTOR
+ && CONST_VECTOR_P (op)
&& !CONST_INT_P (CONST_VECTOR_ELT (op, 0))
&& !CONST_DOUBLE_P (CONST_VECTOR_ELT (op, 0)))
op = unwrap_const_vec_duplicate (op);
@@ -3287,7 +3287,7 @@ static int
const_vector_immediate_p (rtx x)
{
int i;
- gcc_assert (GET_CODE (x) == CONST_VECTOR);
+ gcc_assert (CONST_VECTOR_P (x));
for (i = 0; i < GET_MODE_NUNITS (GET_MODE (x)); i++)
if (!CONST_INT_P (CONST_VECTOR_ELT (x, i))
&& !CONST_DOUBLE_P (CONST_VECTOR_ELT (x, i)))
@@ -3303,9 +3303,9 @@ logical_immediate_p (rtx op, machine_mode mode)
int i, j;
gcc_assert (CONST_INT_P (op) || CONST_DOUBLE_P (op)
- || GET_CODE (op) == CONST_VECTOR);
+ || CONST_VECTOR_P (op));
- if (GET_CODE (op) == CONST_VECTOR
+ if (CONST_VECTOR_P (op)
&& !const_vector_immediate_p (op))
return 0;
@@ -3335,9 +3335,9 @@ iohl_immediate_p (rtx op, machine_mode mode)
int i, j;
gcc_assert (CONST_INT_P (op) || CONST_DOUBLE_P (op)
- || GET_CODE (op) == CONST_VECTOR);
+ || CONST_VECTOR_P (op));
- if (GET_CODE (op) == CONST_VECTOR
+ if (CONST_VECTOR_P (op)
&& !const_vector_immediate_p (op))
return 0;
@@ -3367,9 +3367,9 @@ arith_immediate_p (rtx op, machine_mode mode,
int bytes, i, j;
gcc_assert (CONST_INT_P (op) || CONST_DOUBLE_P (op)
- || GET_CODE (op) == CONST_VECTOR);
+ || CONST_VECTOR_P (op));
- if (GET_CODE (op) == CONST_VECTOR
+ if (CONST_VECTOR_P (op)
&& !const_vector_immediate_p (op))
return 0;
@@ -3408,9 +3408,9 @@ exp2_immediate_p (rtx op, machine_mode mode, int low, int
high)
int bytes, i, j;
gcc_assert (CONST_INT_P (op) || CONST_DOUBLE_P (op)
- || GET_CODE (op) == CONST_VECTOR);
+ || CONST_VECTOR_P (op));
- if (GET_CODE (op) == CONST_VECTOR
+ if (CONST_VECTOR_P (op)
&& !const_vector_immediate_p (op))
return 0;
@@ -3496,7 +3496,7 @@ spu_legitimate_constant_p (machine_mode mode, rtx x)
|| GET_CODE (CONST_VECTOR_ELT (x, 0)) == CONST))
return const_vec_duplicate_p (x);
- if (GET_CODE (x) == CONST_VECTOR
+ if (CONST_VECTOR_P (x)
&& !const_vector_immediate_p (x))
return 0;
return 1;
@@ -5067,7 +5067,7 @@ constant_to_array (machine_mode mode, rtx x, unsigned
char arr[16])
val >>= 8;
}
}
- else if (GET_CODE (x) == CONST_VECTOR)
+ else if (CONST_VECTOR_P (x))
{
int units;
rtx elt;
@@ -6355,7 +6355,7 @@ spu_check_builtin_parm (struct spu_builtin_description
*d, rtx op, int p)
}
else if (CONST_INT_P (op))
v = INTVAL (op);
- else if (GET_CODE (op) == CONST_VECTOR
+ else if (CONST_VECTOR_P (op)
&& CONST_INT_P (CONST_VECTOR_ELT (op, 0)))
v = INTVAL (CONST_VECTOR_ELT (op, 0));
diff --git a/gcc/config/tilegx/tilegx.c b/gcc/config/tilegx/tilegx.c
index cdc7561e54e..b6cf8115c13 100644
--- a/gcc/config/tilegx/tilegx.c
+++ b/gcc/config/tilegx/tilegx.c
@@ -5299,7 +5299,7 @@ tilegx_print_operand (FILE *file, rtx x, int code)
i = INTVAL (x);
else if (CONST_DOUBLE_P (x))
i = CONST_DOUBLE_LOW (x);
- else if (GET_CODE (x) == CONST_VECTOR
+ else if (CONST_VECTOR_P (x)
&& CONST_INT_P (CONST_VECTOR_ELT (x, 0)))
i = INTVAL (CONST_VECTOR_ELT (x, 0));
else
diff --git a/gcc/config/tilepro/tilepro.c b/gcc/config/tilepro/tilepro.c
index 6473ff20fff..f2e24858970 100644
--- a/gcc/config/tilepro/tilepro.c
+++ b/gcc/config/tilepro/tilepro.c
@@ -4619,7 +4619,7 @@ tilepro_print_operand (FILE *file, rtx x, int code)
i = INTVAL (x);
else if (CONST_DOUBLE_P (x))
i = CONST_DOUBLE_LOW (x);
- else if (GET_CODE (x) == CONST_VECTOR
+ else if (CONST_VECTOR_P (x)
&& CONST_INT_P (CONST_VECTOR_ELT (x, 0)))
i = INTVAL (CONST_VECTOR_ELT (x, 0));
else
diff --git a/gcc/dwarf2out.c b/gcc/dwarf2out.c
index 63cb01c8198..c84885a24bb 100644
--- a/gcc/dwarf2out.c
+++ b/gcc/dwarf2out.c
@@ -16813,7 +16813,7 @@ loc_descriptor (rtx rtl, machine_mode mode,
if (mode == VOIDmode
|| CONST_SCALAR_INT_P (XEXP (rtl, 0))
|| CONST_DOUBLE_AS_FLOAT_P (XEXP (rtl, 0))
- || GET_CODE (XEXP (rtl, 0)) == CONST_VECTOR)
+ || CONST_VECTOR_P (XEXP (rtl, 0)))
{
loc_result = loc_descriptor (XEXP (rtl, 0), mode, initialized);
break;
diff --git a/gcc/emit-rtl.c b/gcc/emit-rtl.c
index a667cdab94e..7a811548149 100644
--- a/gcc/emit-rtl.c
+++ b/gcc/emit-rtl.c
@@ -1596,7 +1596,7 @@ gen_lowpart_common (machine_mode mode, rtx x)
return gen_rtx_fmt_e (GET_CODE (x), int_mode, XEXP (x, 0));
}
else if (GET_CODE (x) == SUBREG || REG_P (x)
- || GET_CODE (x) == CONCAT || GET_CODE (x) == CONST_VECTOR
+ || GET_CODE (x) == CONCAT || CONST_VECTOR_P (x)
|| CONST_DOUBLE_AS_FLOAT_P (x) || CONST_SCALAR_INT_P (x)
|| CONST_POLY_INT_P (x))
return lowpart_subreg (mode, x, innermode);
@@ -6004,7 +6004,7 @@ gen_vec_duplicate (machine_mode mode, rtx x)
/* A subroutine of const_vec_series_p that handles the case in which:
- (GET_CODE (X) == CONST_VECTOR
+ (CONST_VECTOR_P (X)
&& CONST_VECTOR_NPATTERNS (X) == 1
&& !CONST_VECTOR_DUPLICATE_P (X))
diff --git a/gcc/explow.c b/gcc/explow.c
index c74c689aead..3253898b66e 100644
--- a/gcc/explow.c
+++ b/gcc/explow.c
@@ -122,7 +122,7 @@ plus_constant (machine_mode mode, rtx x, poly_int64 c, bool
inplace)
{
rtx cst = get_pool_constant (XEXP (x, 0));
- if (GET_CODE (cst) == CONST_VECTOR
+ if (CONST_VECTOR_P (cst)
&& GET_MODE_INNER (GET_MODE (cst)) == mode)
{
cst = gen_lowpart (mode, cst);
diff --git a/gcc/rtlanal.c b/gcc/rtlanal.c
index 7da11b399ba..c33d6cbc967 100644
--- a/gcc/rtlanal.c
+++ b/gcc/rtlanal.c
@@ -2850,7 +2850,7 @@ may_trap_p_1 (const_rtx x, unsigned flags)
return flag_trapping_math;
if (!CONSTANT_P (XEXP (x, 1)) || (XEXP (x, 1) == const0_rtx))
return 1;
- if (GET_CODE (XEXP (x, 1)) == CONST_VECTOR)
+ if (CONST_VECTOR_P (XEXP (x, 1)))
{
/* For CONST_VECTOR, return 1 if any element is or might be zero. */
unsigned int n_elts;
diff --git a/gcc/simplify-rtx.c b/gcc/simplify-rtx.c
index 9359a3cdb4d..603bc456354 100644
--- a/gcc/simplify-rtx.c
+++ b/gcc/simplify-rtx.c
@@ -1736,7 +1736,7 @@ simplify_const_unary_operation (enum rtx_code code,
machine_mode mode,
}
if (CONST_SCALAR_INT_P (op) || CONST_DOUBLE_AS_FLOAT_P (op))
return gen_const_vec_duplicate (mode, op);
- if (GET_CODE (op) == CONST_VECTOR
+ if (CONST_VECTOR_P (op)
&& (CONST_VECTOR_DUPLICATE_P (op)
|| CONST_VECTOR_NUNITS (op).is_constant ()))
{
@@ -1752,7 +1752,7 @@ simplify_const_unary_operation (enum rtx_code code,
machine_mode mode,
}
if (VECTOR_MODE_P (mode)
- && GET_CODE (op) == CONST_VECTOR
+ && CONST_VECTOR_P (op)
&& known_eq (GET_MODE_NUNITS (mode), CONST_VECTOR_NUNITS (op)))
{
gcc_assert (GET_MODE (op) == op_mode);
@@ -3642,7 +3642,7 @@ simplify_binary_operation_1 (enum rtx_code code,
machine_mode mode,
if (vec_duplicate_p (trueop0, &elt0))
return elt0;
- if (GET_CODE (trueop0) == CONST_VECTOR)
+ if (CONST_VECTOR_P (trueop0))
return CONST_VECTOR_ELT (trueop0, INTVAL (XVECEXP
(trueop1, 0, 0)));
@@ -3725,7 +3725,7 @@ simplify_binary_operation_1 (enum rtx_code code,
machine_mode mode,
because they are all the same. */
return gen_vec_duplicate (mode, elt0);
- if (GET_CODE (trueop0) == CONST_VECTOR)
+ if (CONST_VECTOR_P (trueop0))
{
unsigned n_elts = XVECLEN (trueop1, 0);
rtvec v = rtvec_alloc (n_elts);
@@ -3968,10 +3968,10 @@ simplify_binary_operation_1 (enum rtx_code code,
machine_mode mode,
gcc_assert (GET_MODE_INNER (mode) == op1_mode);
unsigned int n_elts, in_n_elts;
- if ((GET_CODE (trueop0) == CONST_VECTOR
+ if ((CONST_VECTOR_P (trueop0)
|| CONST_SCALAR_INT_P (trueop0)
|| CONST_DOUBLE_AS_FLOAT_P (trueop0))
- && (GET_CODE (trueop1) == CONST_VECTOR
+ && (CONST_VECTOR_P (trueop1)
|| CONST_SCALAR_INT_P (trueop1)
|| CONST_DOUBLE_AS_FLOAT_P (trueop1))
&& GET_MODE_NUNITS (mode).is_constant (&n_elts)
@@ -4084,8 +4084,8 @@ simplify_const_binary_operation (enum rtx_code code,
machine_mode mode,
{
if (VECTOR_MODE_P (mode)
&& code != VEC_CONCAT
- && GET_CODE (op0) == CONST_VECTOR
- && GET_CODE (op1) == CONST_VECTOR)
+ && CONST_VECTOR_P (op0)
+ && CONST_VECTOR_P (op1))
{
bool step_ok_p;
if (CONST_VECTOR_STEPPED_P (op0)
@@ -4145,8 +4145,8 @@ simplify_const_binary_operation (enum rtx_code code,
machine_mode mode,
gcc_assert (n_elts >= 2);
if (n_elts == 2)
{
- gcc_assert (GET_CODE (op0) != CONST_VECTOR);
- gcc_assert (GET_CODE (op1) != CONST_VECTOR);
+ gcc_assert (!CONST_VECTOR_P (op0));
+ gcc_assert (!CONST_VECTOR_P (op1));
RTVEC_ELT (v, 0) = op0;
RTVEC_ELT (v, 1) = op1;
@@ -4157,8 +4157,8 @@ simplify_const_binary_operation (enum rtx_code code,
machine_mode mode,
unsigned op1_n_elts = GET_MODE_NUNITS (GET_MODE (op1)).to_constant ();
unsigned i;
- gcc_assert (GET_CODE (op0) == CONST_VECTOR);
- gcc_assert (GET_CODE (op1) == CONST_VECTOR);
+ gcc_assert (CONST_VECTOR_P (op0));
+ gcc_assert (CONST_VECTOR_P (op1));
gcc_assert (op0_n_elts + op1_n_elts == n_elts);
for (i = 0; i < op0_n_elts; ++i)
@@ -5833,7 +5833,7 @@ simplify_ternary_operation (enum rtx_code code,
machine_mode mode,
if (VECTOR_MODE_P (GET_MODE (op1))
&& GET_CODE (op0) == NE
&& GET_CODE (XEXP (op0, 0)) == NOT
- && GET_CODE (XEXP (op0, 1)) == CONST_VECTOR)
+ && CONST_VECTOR_P (XEXP (op0, 1)))
{
rtx cv = XEXP (op0, 1);
int nunits;
@@ -5937,8 +5937,8 @@ simplify_ternary_operation (enum rtx_code code,
machine_mode mode,
rtx trueop0 = avoid_constant_pool_reference (op0);
rtx trueop1 = avoid_constant_pool_reference (op1);
- if (GET_CODE (trueop0) == CONST_VECTOR
- && GET_CODE (trueop1) == CONST_VECTOR)
+ if (CONST_VECTOR_P (trueop0)
+ && CONST_VECTOR_P (trueop1))
{
rtvec v = rtvec_alloc (n_elts);
unsigned int i;
@@ -6001,7 +6001,7 @@ simplify_ternary_operation (enum rtx_code code,
machine_mode mode,
with (vec_concat (X) (B)) if N == 1 or
(vec_concat (A) (X)) if N == 2. */
if (GET_CODE (op0) == VEC_DUPLICATE
- && GET_CODE (op1) == CONST_VECTOR
+ && CONST_VECTOR_P (op1)
&& known_eq (CONST_VECTOR_NUNITS (op1), 2)
&& known_eq (GET_MODE_NUNITS (GET_MODE (op0)), 2)
&& IN_RANGE (sel, 1, 2))
@@ -6177,7 +6177,7 @@ simplify_immed_subreg (fixed_size_mode outermode, rtx op,
/* Unpack the value. */
- if (GET_CODE (op) == CONST_VECTOR)
+ if (CONST_VECTOR_P (op))
{
num_elem = CEIL (inner_bytes, GET_MODE_UNIT_SIZE (innermode));
elem_bitsize = GET_MODE_UNIT_BITSIZE (innermode);
@@ -6195,7 +6195,7 @@ simplify_immed_subreg (fixed_size_mode outermode, rtx op,
for (elem = 0; elem < num_elem; elem++)
{
unsigned char * vp;
- rtx el = (GET_CODE (op) == CONST_VECTOR
+ rtx el = (CONST_VECTOR_P (op)
? CONST_VECTOR_ELT (op, first_elem + elem)
: op);
@@ -6511,7 +6511,7 @@ simplify_subreg (machine_mode outermode, rtx op,
if (CONST_SCALAR_INT_P (op)
|| CONST_DOUBLE_AS_FLOAT_P (op)
|| CONST_FIXED_P (op)
- || GET_CODE (op) == CONST_VECTOR)
+ || CONST_VECTOR_P (op))
{
/* simplify_immed_subreg deconstructs OP into bytes and constructs
the result from bytes, so it only works if the sizes of the modes
@@ -6528,7 +6528,7 @@ simplify_subreg (machine_mode outermode, rtx op,
/* Handle constant-sized outer modes and variable-sized inner modes. */
unsigned HOST_WIDE_INT first_elem;
- if (GET_CODE (op) == CONST_VECTOR
+ if (CONST_VECTOR_P (op)
&& is_a <fixed_size_mode> (outermode, &fs_outermode)
&& constant_multiple_p (byte, GET_MODE_UNIT_SIZE (innermode),
&first_elem))
diff --git a/gcc/varasm.c b/gcc/varasm.c
index 0e833b9bc58..e6263f09226 100644
--- a/gcc/varasm.c
+++ b/gcc/varasm.c
@@ -3973,7 +3973,7 @@ output_constant_pool_2 (fixed_size_mode mode, rtx x,
unsigned int align)
case MODE_VECTOR_BOOL:
{
- gcc_assert (GET_CODE (x) == CONST_VECTOR);
+ gcc_assert (CONST_VECTOR_P (x));
/* Pick the smallest integer mode that contains at least one
whole element. Often this is byte_mode and contains more
@@ -4008,7 +4008,7 @@ output_constant_pool_2 (fixed_size_mode mode, rtx x,
unsigned int align)
scalar_mode submode = GET_MODE_INNER (mode);
unsigned int subalign = MIN (align, GET_MODE_BITSIZE (submode));
- gcc_assert (GET_CODE (x) == CONST_VECTOR);
+ gcc_assert (CONST_VECTOR_P (x));
units = GET_MODE_NUNITS (mode);
for (i = 0; i < units; i++)
--
2.21.0
