This is patch #19. It is a fairly simple patch to clone the power9 costs and
use that for costs on the 'future' machine.
As I write this message, I am waiting for the full bootstrap and make of the
patch on a little endian power8 system. Assuming there are no regressions, can
I check this into the FSF trunk?
iThis is a series of separate patches to add functionality to the PowerPC
backend to support future processors. Here is a high level summary of the
patches:
* Patches 1-8, have already been applied
* Patch 9 has been rewritten in patches 12-13
* Patch 10 is withdrawn for now
* Patch 11 adds DS offset mode to rs6000.c's reg_addr
* Patch 12 adds a new enumeration for instruction format
* Patch 13 adds support for matching prefixed insns
* Patch 14 adds pc-relative support to load up addresses
* Patch 15 renamed some functions to be smaller
* Patch 16 updated a comment and moved a predicate
* Patch 17 adds the prefixed RTL attribute & emitting 'p' before prefixed
* Patch 18 adds prefixed support for scalar types
* Patch 19 uses a separate 'future' cost structure
* Patch 20 clones power9.md for initial scheduling on future.md.
The following patches have not yet been written, but I expect them to be:
* Patch 21 finish prefixed insn support for vectors & 128-bit int/floats
* Patch 22 enable pc-relative by default
* Patch 23 add pcrel linker optimization
* Patch 24 new tests
2019-07-25 Michael Meissner <meiss...@linux.ibm.com>
* config/rs6000/rs6000.c (future_cost): New cost structure.
(rs6000_option_override_internal): Use future cost structure.
Index: gcc/config/rs6000/rs6000.c
===================================================================
--- gcc/config/rs6000/rs6000.c (revision 273815)
+++ gcc/config/rs6000/rs6000.c (working copy)
@@ -1094,6 +1094,26 @@ struct processor_costs power9_cost = {
COSTS_N_INSNS (3), /* SF->DF convert */
};
+/* Instruction costs on FUTURE processors. */
+static const
+struct processor_costs future_cost = {
+ COSTS_N_INSNS (3), /* mulsi */
+ COSTS_N_INSNS (3), /* mulsi_const */
+ COSTS_N_INSNS (3), /* mulsi_const9 */
+ COSTS_N_INSNS (3), /* muldi */
+ COSTS_N_INSNS (8), /* divsi */
+ COSTS_N_INSNS (12), /* divdi */
+ COSTS_N_INSNS (3), /* fp */
+ COSTS_N_INSNS (3), /* dmul */
+ COSTS_N_INSNS (13), /* sdiv */
+ COSTS_N_INSNS (18), /* ddiv */
+ 128, /* cache line size */
+ 32, /* l1 cache */
+ 512, /* l2 cache */
+ 8, /* prefetch streams */
+ COSTS_N_INSNS (3), /* SF->DF convert */
+};
+
/* Instruction costs on POWER A2 processors. */
static const
struct processor_costs ppca2_cost = {
@@ -4622,10 +4642,13 @@ rs6000_option_override_internal (bool gl
break;
case PROCESSOR_POWER9:
- case PROCESSOR_FUTURE:
rs6000_cost = &power9_cost;
break;
+ case PROCESSOR_FUTURE:
+ rs6000_cost = &future_cost;
+ break;
+
case PROCESSOR_PPCA2:
rs6000_cost = &ppca2_cost;
break;
--
Michael Meissner, IBM
IBM, M/S 2506R, 550 King Street, Littleton, MA 01460-6245, USA
email: meiss...@linux.ibm.com, phone: +1 (978) 899-4797
