On Thu, Jul 18, 2019 at 04:26:26PM +0100, Richard Earnshaw (lists) wrote:
>
>
> On 18/07/2019 16:17, Jakub Jelinek wrote:
> > On Thu, Jul 18, 2019 at 04:12:48PM +0100, Richard Earnshaw (lists) wrote:
> > > > Both directions:
> > > > aarch64 c6x ia64 m68k nios2 parisc sh x86 xtensa
> > >
> > > AArch64 is Right only.
> >
> > Maybe hw-wise, but it has both rotr<mode>3 and rotl<mode>3 expanders.
> > At least for GPRs.
> >
> > Jakub
> >
>
> Only for immediates. And the patterns that support that just write out
> assembly as "ror (<size> - n)".
For registers too (for those it negates and uses rotr).
Note, the middle-end ought to be able to do the same thing already,
except if not SHIFT_COUNT_TRUNCATED it will use bits - count instead of
-count.
(define_expand "rotl<mode>3"
[(set (match_operand:GPI 0 "register_operand")
(rotatert:GPI (match_operand:GPI 1 "register_operand")
(match_operand:QI 2 "aarch64_reg_or_imm")))]
""
{
/* (SZ - cnt) % SZ == -cnt % SZ */
if (CONST_INT_P (operands[2]))
{
operands[2] = GEN_INT ((-INTVAL (operands[2]))
& (GET_MODE_BITSIZE (<MODE>mode) - 1));
if (operands[2] == const0_rtx)
{
emit_insn (gen_mov<mode> (operands[0], operands[1]));
DONE;
}
}
else
operands[2] = expand_simple_unop (QImode, NEG, operands[2],
NULL_RTX, 1);
}
)
Jakub
