* Claudiu Zissulescu <claz...@gmail.com> [2019-03-25 12:03:13 +0100]:
> New LRA algorithms require the all the register constraints to be
> defined using define_register_constraint keyword. However, Rs5
> constraint was not LRA proof. Remove it and replace it by equivalent
> Rcd constraint.
>
> gcc/
> xxxx-xx-xx Claudiu Zissulescu <claz...@synopsys.com>
>
> * config/arc/arc.md (sibcall_insn): Use Rcd constraint.
> (sibcall_value_insn): Likewise.
> * config/arc/constraints.md (Rs5): Remove.
This is fine.
thanks,
Andrew
> ---
> gcc/config/arc/arc.md | 24 +++++++++++------------
> gcc/config/arc/constraints.md | 10 ----------
> gcc/testsuite/gcc.target/arc/long-calls.c | 4 ++--
> 3 files changed, 14 insertions(+), 24 deletions(-)
>
> diff --git a/gcc/config/arc/arc.md b/gcc/config/arc/arc.md
> index 7ac5a1b5785..54d073107a8 100644
> --- a/gcc/config/arc/arc.md
> +++ b/gcc/config/arc/arc.md
> @@ -4703,17 +4703,17 @@ core_3, archs4x, archs4xd, archs4xd_slow"
>
> (define_insn "*sibcall_insn"
> [(call (mem:SI (match_operand:SI 0 "call_address_operand"
> - "Cbp,Cbr,Rs5,Rsc,Cal"))
> + "Cbp,Cbr,!Rcd,Rsc,Cal"))
> (match_operand 1 "" ""))
> (simple_return)
> (use (match_operand 2 "" ""))]
> ""
> "@
> - b%!%* %P0
> - b%!%* %P0
> - j%!%* [%0]%&
> - j%!%* [%0]
> - j%! %P0"
> + b%!%*\\t%P0
> + b%!%*\\t%P0
> + j%!%*\\t[%0]
> + j%!%*\\t[%0]
> + j%!\\t%P0"
> [(set_attr "type" "call,call,call,call,call_no_delay_slot")
> (set_attr "predicable" "yes,no,no,yes,yes")
> (set_attr "iscompact" "false,false,maybe,false,false")
> @@ -4723,17 +4723,17 @@ core_3, archs4x, archs4xd, archs4xd_slow"
> (define_insn "*sibcall_value_insn"
> [(set (match_operand 0 "dest_reg_operand" "")
> (call (mem:SI (match_operand:SI 1 "call_address_operand"
> - "Cbp,Cbr,Rs5,Rsc,Cal"))
> + "Cbp,Cbr,!Rcd,Rsc,Cal"))
> (match_operand 2 "" "")))
> (simple_return)
> (use (match_operand 3 "" ""))]
> ""
> "@
> - b%!%* %P1
> - b%!%* %P1
> - j%!%* [%1]%&
> - j%!%* [%1]
> - j%! %P1"
> + b%!%*\\t%P1
> + b%!%*\\t%P1
> + j%!%*\\t[%1]
> + j%!%*\\t[%1]
> + j%!\\t%P1"
> [(set_attr "type" "call,call,call,call,call_no_delay_slot")
> (set_attr "predicable" "yes,no,no,yes,yes")
> (set_attr "iscompact" "false,false,maybe,false,false")
> diff --git a/gcc/config/arc/constraints.md b/gcc/config/arc/constraints.md
> index 523210432da..494e4792316 100644
> --- a/gcc/config/arc/constraints.md
> +++ b/gcc/config/arc/constraints.md
> @@ -480,16 +480,6 @@
> (and (match_code "reg")
> (match_test "REGNO (op) == 31")))
>
> -(define_constraint "Rs5"
> - "@internal
> - sibcall register - only allow one of the five available 16 bit isnsn.
> - Registers usable in ARCompact 16-bit instructions: @code{r0}-@code{r3},
> - @code{r12}"
> - (and (match_code "reg")
> - (match_test "!arc_ccfsm_cond_exec_p ()")
> - (ior (match_test "(unsigned) REGNO (op) <= 3")
> - (match_test "REGNO (op) == 12"))))
> -
> (define_constraint "Rcc"
> "@internal
> Condition Codes"
> diff --git a/gcc/testsuite/gcc.target/arc/long-calls.c
> b/gcc/testsuite/gcc.target/arc/long-calls.c
> index 63fafbcc674..9ae36ca0df3 100644
> --- a/gcc/testsuite/gcc.target/arc/long-calls.c
> +++ b/gcc/testsuite/gcc.target/arc/long-calls.c
> @@ -5,7 +5,7 @@ int g (void);
>
> int f (void)
> {
> - g();
> + g();
> }
>
> -/* { dg-final { scan-assembler "j @g" } } */
> +/* { dg-final { scan-assembler "j\\t@g" } } */
> --
> 2.20.1
>
