gcc/ChangeLog: 2019-04-02 Andreas Krebbel <kreb...@linux.ibm.com>
* config/s390/s390.md (VX_CONV_BFP, VX_CONV_INT): New mode iterators. (SFSI): New mode attribute. ("*fixuns_truncdfdi2_vx", "*fix_truncdfdi2_bfp_z13") ("*floatunsdidf2_z13", ): Add support for 32 bit conversions and rename to ... ("*fixuns_trunc<VX_CONV_BFP:mode><VX_CONV_INT:mode>2_z13") ("*fix_trunc<VX_CONV_BFP:mode><VX_CONV_INT:mode>2_bfp_z13") ("*floatuns<VX_CONV_INT:mode><VX_CONV_BFP:mode>2_z13"): ... these. ("floatsi<mode>2"): Add wcefb instruction. --- gcc/config/s390/s390.md | 71 ++++++++++++++++++++++++++++++------------------- 1 file changed, 44 insertions(+), 27 deletions(-) diff --git a/gcc/config/s390/s390.md b/gcc/config/s390/s390.md index d227b26..17aafe5 100644 --- a/gcc/config/s390/s390.md +++ b/gcc/config/s390/s390.md @@ -632,6 +632,10 @@ (define_mode_iterator DD_DF [DF DD]) (define_mode_iterator TD_TF [TF TD]) +; 32 bit int<->fp conversion instructions are available since VXE2 (arch13). +(define_mode_iterator VX_CONV_BFP [DF (SF "TARGET_VXE2")]) +(define_mode_iterator VX_CONV_INT [DI (SI "TARGET_VXE2")]) + ;; These mode iterators allow 31-bit and 64-bit GPR patterns to be generated ;; from the same template. (define_mode_iterator GPR [(DI "TARGET_ZARCH") SI]) @@ -724,6 +728,9 @@ (define_mode_attr DFDI [(TF "0") (DF "*") (SF "0") (TD "0") (DD "0") (DD "0") (TI "0") (DI "*") (SI "0")]) +(define_mode_attr SFSI [(TF "0") (DF "0") (SF "*") + (TD "0") (DD "0") (DD "0") + (TI "0") (DI "0") (SI "*")]) (define_mode_attr DF [(TF "0") (DF "*") (SF "0") (TD "0") (DD "0") (DD "0") (TI "0") (DI "0") (SI "0")]) @@ -5053,16 +5060,18 @@ ; fixuns_trunc(tf|df|sf|td|dd)(di|si)2 instruction patterns. -; df -> unsigned di -(define_insn "*fixuns_truncdfdi2_vx" - [(set (match_operand:DI 0 "register_operand" "=d,v") - (unsigned_fix:DI (match_operand:DF 1 "register_operand" "f,v"))) - (unspec:DI [(match_operand:DI 2 "immediate_operand" "K,K")] UNSPEC_ROUND) +; df -> unsigned di, vxe2: sf -> unsigned si +; clgdbr, clfebr, wclgdb, wclfeb +(define_insn "*fixuns_trunc<VX_CONV_BFP:mode><VX_CONV_INT:mode>2_z13" + [(set (match_operand:VX_CONV_INT 0 "register_operand" "=d,v") + (unsigned_fix:VX_CONV_INT (match_operand:VX_CONV_BFP 1 "register_operand" "f,v"))) + (unspec:DI [(match_operand:DI 2 "immediate_operand" "K,K")] UNSPEC_ROUND) (clobber (reg:CC CC_REGNUM))] - "TARGET_VX && TARGET_HARD_FLOAT" + "TARGET_VX && TARGET_HARD_FLOAT + && GET_MODE_SIZE (<VX_CONV_INT:MODE>mode) == GET_MODE_SIZE (<VX_CONV_BFP:MODE>mode)" "@ - clgdbr\t%0,%h2,%1,0 - wclgdb\t%v0,%v1,0,%h2" + cl<VX_CONV_INT:gf><VX_CONV_BFP:xde>br\t%0,%h2,%1,0 + wcl<VX_CONV_INT:gf><VX_CONV_BFP:xde>b\t%v0,%v1,0,%h2" [(set_attr "op_type" "RRF,VRR") (set_attr "type" "ftoi")]) @@ -5090,15 +5099,18 @@ DONE; }) -(define_insn "*fix_truncdfdi2_bfp_z13" - [(set (match_operand:DI 0 "register_operand" "=d,v") - (fix:DI (match_operand:DF 1 "register_operand" "f,v"))) - (unspec:DI [(match_operand:DI 2 "immediate_operand" "K,K")] UNSPEC_ROUND) +; df -> signed di, vxe2: sf -> signed si +; cgdbr, cfebr, wcgdb, wcfeb +(define_insn "*fix_trunc<VX_CONV_BFP:mode><VX_CONV_INT:mode>2_bfp_z13" + [(set (match_operand:VX_CONV_INT 0 "register_operand" "=d,v") + (fix:VX_CONV_INT (match_operand:VX_CONV_BFP 1 "register_operand" "f,v"))) + (unspec:VX_CONV_INT [(match_operand:VX_CONV_INT 2 "immediate_operand" "K,K")] UNSPEC_ROUND) (clobber (reg:CC CC_REGNUM))] - "TARGET_VX && TARGET_HARD_FLOAT" + "TARGET_VX && TARGET_HARD_FLOAT + && GET_MODE_SIZE (<VX_CONV_INT:MODE>mode) == GET_MODE_SIZE (<VX_CONV_BFP:MODE>mode)" "@ - cgdbr\t%0,%h2,%1 - wcgdb\t%v0,%v1,0,%h2" + c<VX_CONV_INT:gf><VX_CONV_BFP:xde>br\t%0,%h2,%1 + wc<VX_CONV_INT:gf><VX_CONV_BFP:xde>b\t%v0,%v1,0,%h2" [(set_attr "op_type" "RRE,VRR") (set_attr "type" "ftoi")]) @@ -5178,14 +5190,18 @@ (set_attr "cpu_facility" "*,vx") (set_attr "enabled" "*,<DFDI>")]) -; cxfbr, cdfbr, cefbr +; cxfbr, cdfbr, cefbr, wcefb (define_insn "floatsi<mode>2" - [(set (match_operand:BFP 0 "register_operand" "=f") - (float:BFP (match_operand:SI 1 "register_operand" "d")))] + [(set (match_operand:BFP 0 "register_operand" "=f,v") + (float:BFP (match_operand:SI 1 "register_operand" "d,v")))] "TARGET_HARD_FLOAT" - "c<xde>fbr\t%0,%1" - [(set_attr "op_type" "RRE") - (set_attr "type" "itof<mode>" )]) + "@ + c<xde>fbr\t%0,%1 + wcefb\t%v0,%v1,0,0" + [(set_attr "op_type" "RRE,VRR") + (set_attr "type" "itof<mode>" ) + (set_attr "cpu_facility" "*,vxe2") + (set_attr "enabled" "*,<SFSI>")]) ; cxftr, cdftr (define_insn "floatsi<mode>2" @@ -5200,13 +5216,14 @@ ; floatuns(si|di)(tf|df|sf|td|dd)2 instruction pattern(s). ; -(define_insn "*floatunsdidf2_z13" - [(set (match_operand:DF 0 "register_operand" "=f,v") - (unsigned_float:DF (match_operand:DI 1 "register_operand" "d,v")))] - "TARGET_VX && TARGET_HARD_FLOAT" +(define_insn "*floatuns<VX_CONV_INT:mode><VX_CONV_BFP:mode>2_z13" + [(set (match_operand:VX_CONV_BFP 0 "register_operand" "=f,v") + (unsigned_float:VX_CONV_BFP (match_operand:VX_CONV_INT 1 "register_operand" "d,v")))] + "TARGET_VX && TARGET_HARD_FLOAT + && GET_MODE_SIZE (<VX_CONV_INT:MODE>mode) == GET_MODE_SIZE (<VX_CONV_BFP:MODE>mode)" "@ - cdlgbr\t%0,0,%1,0 - wcdlgb\t%v0,%v1,0,0" + c<VX_CONV_BFP:xde>l<VX_CONV_INT:gf>br\t%0,0,%1,0 + wc<VX_CONV_BFP:xde>l<VX_CONV_INT:gf>b\t%v0,%v1,0,0" [(set_attr "op_type" "RRE,VRR") (set_attr "type" "itofdf")]) -- 2.7.4