On Thu, Feb 21, 2019 at 3:25 PM H.J. Lu <[email protected]> wrote:
>
> On Thu, Feb 21, 2019 at 3:10 PM Thiago Macieira
> <[email protected]> wrote:
> >
> > This is a repeat of commit r263989, which commit r264052 accidentally
> > reverted.
> >
> > Original commit message:
> >
> > The instruction set first appeared with Westmere, but not all processors
> > in that and the next few generations have the instructions. According to
> > Wikipedia[1], the first generation in which all SKUs have AES
> > instructions are Skylake and Goldmont. I can't find any Skylake,
> > Kabylake, Kabylake-R or Cannon Lake currently listed at
> > https://ark.intel.com that says "Intel® AES New Instructions" "No".
> >
> > [1] https://en.wikipedia.org/wiki/AES_instruction_set
> >
> > 2018-08-30 Thiago Macieira <[email protected]>
> >
> > * config/i386/i386.c (PTA_WESTMERE): Remove PTA_AES.
> > (PTA_SKYLAKE): Add PTA_AES.
> > (PTA_GOLDMONT): Likewise.
>
> I opened:
>
> https://gcc.gnu.org/bugzilla/show_bug.cgi?id=89444
>
> and I will check it in for Thiago tomorrow.
>
Now, r263989 has been re-applied. I got
FAIL: g++.target/i386/mv16.C -std=gnu++14 execution test
FAIL: g++.target/i386/mv16.C -std=gnu++17 execution test
FAIL: g++.target/i386/mv16.C -std=gnu++98 execution test
On Westmere. Shouldn't this
case PROCESSOR_NEHALEM:
if (new_target->x_ix86_isa_flags & OPTION_MASK_ISA_AES)
{
arg_str = "westmere";
priority = P_AES;
}
else
be removed?
--
H.J.
