On Tue, Feb 12, 2019 at 4:07 AM Uros Bizjak <[email protected]> wrote:
>
> On Mon, Feb 11, 2019 at 11:55 PM H.J. Lu <[email protected]> wrote:
> >
> > Allow MMX intrinsic emulation with SSE/SSE2/SSSE3. Don't enable MMX ISA
> > by default with TARGET_MMX_WITH_SSE.
> >
> > For pr82483-1.c and pr82483-2.c, "-mssse3 -mno-mmx" compiles in 64-bit
> > mode since MMX intrinsics can be emulated wit SSE.
> >
> > gcc/
> >
> > PR target/89021
> > * config/i386/i386-builtin.def: Enable MMX intrinsics with
> > SSE/SSE2/SSSE3.
> > * config/i386/i386.c (ix86_option_override_internal): Don't
> > enable MMX ISA with TARGET_MMX_WITH_SSE by default.
> > (bdesc_tm): Enable MMX intrinsics with SSE/SSE2/SSSE3.
> > (ix86_init_mmx_sse_builtins): Likewise.
> > (ix86_expand_builtin): Allow SSE/SSE2/SSSE3 to emulate MMX
> > intrinsics with TARGET_MMX_WITH_SSE.
> > * config/i386/mmintrin.h: Don't require MMX in 64-bit mode.
> >
> > gcc/testsuite/
> >
> > PR target/89021
> > * gcc.target/i386/pr82483-1.c: Error only on ia32.
> > * gcc.target/i386/pr82483-2.c: Likewise.
> > ---
> > gcc/config/i386/i386-builtin.def | 126 +++++++++++-----------
> > gcc/config/i386/i386.c | 62 +++++++----
> > gcc/config/i386/mmintrin.h | 10 +-
> > gcc/testsuite/gcc.target/i386/pr82483-1.c | 2 +-
> > gcc/testsuite/gcc.target/i386/pr82483-2.c | 2 +-
> > 5 files changed, 118 insertions(+), 84 deletions(-)
> >
> > @@ -30810,13 +30815,13 @@ static const struct builtin_description
> > bdesc_##kind[] = \
> > we're lazy. Add casts to make them fit. */
> > static const struct builtin_description bdesc_tm[] =
> > {
> > - { OPTION_MASK_ISA_MMX, 0, CODE_FOR_nothing, "__builtin__ITM_WM64", (enum
> > ix86_builtins) BUILT_IN_TM_STORE_M64, UNKNOWN, VOID_FTYPE_PV2SI_V2SI },
> > - { OPTION_MASK_ISA_MMX, 0, CODE_FOR_nothing, "__builtin__ITM_WaRM64",
> > (enum ix86_builtins) BUILT_IN_TM_STORE_WAR_M64, UNKNOWN,
> > VOID_FTYPE_PV2SI_V2SI },
> > - { OPTION_MASK_ISA_MMX, 0, CODE_FOR_nothing, "__builtin__ITM_WaWM64",
> > (enum ix86_builtins) BUILT_IN_TM_STORE_WAW_M64, UNKNOWN,
> > VOID_FTYPE_PV2SI_V2SI },
> > - { OPTION_MASK_ISA_MMX, 0, CODE_FOR_nothing, "__builtin__ITM_RM64", (enum
> > ix86_builtins) BUILT_IN_TM_LOAD_M64, UNKNOWN, V2SI_FTYPE_PCV2SI },
> > - { OPTION_MASK_ISA_MMX, 0, CODE_FOR_nothing, "__builtin__ITM_RaRM64",
> > (enum ix86_builtins) BUILT_IN_TM_LOAD_RAR_M64, UNKNOWN, V2SI_FTYPE_PCV2SI },
> > - { OPTION_MASK_ISA_MMX, 0, CODE_FOR_nothing, "__builtin__ITM_RaWM64",
> > (enum ix86_builtins) BUILT_IN_TM_LOAD_RAW_M64, UNKNOWN, V2SI_FTYPE_PCV2SI },
> > - { OPTION_MASK_ISA_MMX, 0, CODE_FOR_nothing, "__builtin__ITM_RfWM64",
> > (enum ix86_builtins) BUILT_IN_TM_LOAD_RFW_M64, UNKNOWN, V2SI_FTYPE_PCV2SI },
> > + { OPTION_MASK_ISA_MMX | OPTION_MASK_ISA_SSE2, 0, CODE_FOR_nothing,
> > "__builtin__ITM_WM64", (enum ix86_builtins) BUILT_IN_TM_STORE_M64, UNKNOWN,
> > VOID_FTYPE_PV2SI_V2SI },
> > + { OPTION_MASK_ISA_MMX | OPTION_MASK_ISA_SSE2, 0, CODE_FOR_nothing,
> > "__builtin__ITM_WaRM64", (enum ix86_builtins) BUILT_IN_TM_STORE_WAR_M64,
> > UNKNOWN, VOID_FTYPE_PV2SI_V2SI },
> > + { OPTION_MASK_ISA_MMX | OPTION_MASK_ISA_SSE2, 0, CODE_FOR_nothing,
> > "__builtin__ITM_WaWM64", (enum ix86_builtins) BUILT_IN_TM_STORE_WAW_M64,
> > UNKNOWN, VOID_FTYPE_PV2SI_V2SI },
> > + { OPTION_MASK_ISA_MMX | OPTION_MASK_ISA_SSE2, 0, CODE_FOR_nothing,
> > "__builtin__ITM_RM64", (enum ix86_builtins) BUILT_IN_TM_LOAD_M64, UNKNOWN,
> > V2SI_FTYPE_PCV2SI },
> > + { OPTION_MASK_ISA_MMX | OPTION_MASK_ISA_SSE2, 0, CODE_FOR_nothing,
> > "__builtin__ITM_RaRM64", (enum ix86_builtins) BUILT_IN_TM_LOAD_RAR_M64,
> > UNKNOWN, V2SI_FTYPE_PCV2SI },
> > + { OPTION_MASK_ISA_MMX | OPTION_MASK_ISA_SSE2, 0, CODE_FOR_nothing,
> > "__builtin__ITM_RaWM64", (enum ix86_builtins) BUILT_IN_TM_LOAD_RAW_M64,
> > UNKNOWN, V2SI_FTYPE_PCV2SI },
> > + { OPTION_MASK_ISA_MMX | OPTION_MASK_ISA_SSE2, 0, CODE_FOR_nothing,
> > "__builtin__ITM_RfWM64", (enum ix86_builtins) BUILT_IN_TM_LOAD_RFW_M64,
> > UNKNOWN, V2SI_FTYPE_PCV2SI },
>
> Please explain why you need the above change.
Reverted.
> > { OPTION_MASK_ISA_SSE, 0, CODE_FOR_nothing, "__builtin__ITM_WM128",
> > (enum ix86_builtins) BUILT_IN_TM_STORE_M128, UNKNOWN, VOID_FTYPE_PV4SF_V4SF
> > },
> > { OPTION_MASK_ISA_SSE, 0, CODE_FOR_nothing, "__builtin__ITM_WaRM128",
> > (enum ix86_builtins) BUILT_IN_TM_STORE_WAR_M128, UNKNOWN,
> > VOID_FTYPE_PV4SF_V4SF },
> > @@ -30834,7 +30839,7 @@ static const struct builtin_description bdesc_tm[] =
> > { OPTION_MASK_ISA_AVX, 0, CODE_FOR_nothing, "__builtin__ITM_RaWM256",
> > (enum ix86_builtins) BUILT_IN_TM_LOAD_RAW_M256, UNKNOWN, V8SF_FTYPE_PCV8SF
> > },
> > { OPTION_MASK_ISA_AVX, 0, CODE_FOR_nothing, "__builtin__ITM_RfWM256",
> > (enum ix86_builtins) BUILT_IN_TM_LOAD_RFW_M256, UNKNOWN, V8SF_FTYPE_PCV8SF
> > },
> >
> > - { OPTION_MASK_ISA_MMX, 0, CODE_FOR_nothing, "__builtin__ITM_LM64", (enum
> > ix86_builtins) BUILT_IN_TM_LOG_M64, UNKNOWN, VOID_FTYPE_PCVOID },
> > + { OPTION_MASK_ISA_MMX | OPTION_MASK_ISA_SSE2, 0, CODE_FOR_nothing,
> > "__builtin__ITM_LM64", (enum ix86_builtins) BUILT_IN_TM_LOG_M64, UNKNOWN,
> > VOID_FTYPE_PCVOID },
> > { OPTION_MASK_ISA_SSE, 0, CODE_FOR_nothing, "__builtin__ITM_LM128",
> > (enum ix86_builtins) BUILT_IN_TM_LOG_M128, UNKNOWN, VOID_FTYPE_PCVOID },
> > { OPTION_MASK_ISA_AVX, 0, CODE_FOR_nothing, "__builtin__ITM_LM256",
> > (enum ix86_builtins) BUILT_IN_TM_LOG_M256, UNKNOWN, VOID_FTYPE_PCVOID },
> > };
> > @@ -31509,14 +31514,17 @@ ix86_init_mmx_sse_builtins (void)
> > VOID_FTYPE_UNSIGNED, IX86_BUILTIN_XABORT);
> >
> > /* MMX access to the vec_init patterns. */
> > - def_builtin_const (OPTION_MASK_ISA_MMX, 0,
> > "__builtin_ia32_vec_init_v2si",
> > + def_builtin_const (OPTION_MASK_ISA_MMX | OPTION_MASK_ISA_SSE2, 0,
> > + "__builtin_ia32_vec_init_v2si",
> > V2SI_FTYPE_INT_INT, IX86_BUILTIN_VEC_INIT_V2SI);
> >
> > - def_builtin_const (OPTION_MASK_ISA_MMX, 0,
> > "__builtin_ia32_vec_init_v4hi",
> > + def_builtin_const (OPTION_MASK_ISA_MMX | OPTION_MASK_ISA_SSE2, 0,
> > + "__builtin_ia32_vec_init_v4hi",
> > V4HI_FTYPE_HI_HI_HI_HI,
> > IX86_BUILTIN_VEC_INIT_V4HI);
> >
> > - def_builtin_const (OPTION_MASK_ISA_MMX, 0,
> > "__builtin_ia32_vec_init_v8qi",
> > + def_builtin_const (OPTION_MASK_ISA_MMX | OPTION_MASK_ISA_SSE2, 0,
> > + "__builtin_ia32_vec_init_v8qi",
> > V8QI_FTYPE_QI_QI_QI_QI_QI_QI_QI_QI,
> > IX86_BUILTIN_VEC_INIT_V8QI);
> >
> > @@ -31538,7 +31546,8 @@ ix86_init_mmx_sse_builtins (void)
> > "__builtin_ia32_vec_ext_v4hi",
> > HI_FTYPE_V4HI_INT, IX86_BUILTIN_VEC_EXT_V4HI);
> >
> > - def_builtin_const (OPTION_MASK_ISA_MMX, 0, "__builtin_ia32_vec_ext_v2si",
> > + def_builtin_const (OPTION_MASK_ISA_MMX | OPTION_MASK_ISA_SSE2, 0,
> > + "__builtin_ia32_vec_ext_v2si",
> > SI_FTYPE_V2SI_INT, IX86_BUILTIN_VEC_EXT_V2SI);
> >
> > def_builtin_const (OPTION_MASK_ISA_SSE2, 0,
> > "__builtin_ia32_vec_ext_v16qi",
> > @@ -36671,6 +36680,23 @@ ix86_expand_builtin (tree exp, rtx target, rtx
> > subtarget,
> > == (OPTION_MASK_ISA_FMA | OPTION_MASK_ISA_FMA4))
> > && (isa & (OPTION_MASK_ISA_FMA | OPTION_MASK_ISA_FMA4)) != 0)
> > isa |= (OPTION_MASK_ISA_FMA | OPTION_MASK_ISA_FMA4);
> > + /* Use SSE/SSE2/SSSE3 to emulate MMX intrinsics in 64-bit mode when
> > + MMX is disabled. */
> > + if (TARGET_MMX_WITH_SSE)
> > + {
> > + if (((bisa & (OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_MMX))
> > + == (OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_MMX))
> > + && (isa & (OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_MMX)) != 0)
> > + isa |= (OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_MMX);
> > + if (((bisa & (OPTION_MASK_ISA_SSE2 | OPTION_MASK_ISA_MMX))
> > + == (OPTION_MASK_ISA_SSE2 | OPTION_MASK_ISA_MMX))
> > + && (isa & (OPTION_MASK_ISA_SSE2 | OPTION_MASK_ISA_MMX)) != 0)
> > + isa |= (OPTION_MASK_ISA_SSE2 | OPTION_MASK_ISA_MMX);
> > + if (((bisa & (OPTION_MASK_ISA_SSSE3 | OPTION_MASK_ISA_MMX))
> > + == (OPTION_MASK_ISA_SSSE3 | OPTION_MASK_ISA_MMX))
> > + && (isa & (OPTION_MASK_ISA_SSSE3 | OPTION_MASK_ISA_MMX)) != 0)
> > + isa |= (OPTION_MASK_ISA_SSSE3 | OPTION_MASK_ISA_MMX);
> > + }
> > if ((bisa & isa) != bisa || (bisa2 & isa2) != bisa2)
> > {
> > char *opts = ix86_target_string (bisa, bisa2, 0, 0, NULL, NULL,
> > diff --git a/gcc/config/i386/mmintrin.h b/gcc/config/i386/mmintrin.h
> > index 238b3df3121..7b613658111 100644
> > --- a/gcc/config/i386/mmintrin.h
> > +++ b/gcc/config/i386/mmintrin.h
> > @@ -30,7 +30,7 @@
> > #if defined __x86_64__ && !defined __SSE__ || !defined __MMX__
> > #pragma GCC push_options
> > #ifdef __x86_64__
> > -#pragma GCC target("sse,mmx")
> > +#pragma GCC target("sse2")
> > #else
> > #pragma GCC target("mmx")
> > #endif
> > @@ -315,7 +315,11 @@ _m_paddd (__m64 __m1, __m64 __m2)
> > /* Add the 64-bit values in M1 to the 64-bit values in M2. */
> > #ifndef __SSE2__
> > #pragma GCC push_options
> > +#ifdef __x86_64__
> > +#pragma GCC target("sse2")
> > +#else
> > #pragma GCC target("sse2,mmx")
> > +#endif
> > #define __DISABLE_SSE2__
> > #endif /* __SSE2__ */
> > @@ -427,7 +431,11 @@ _m_psubd (__m64 __m1, __m64 __m2)
> > /* Add the 64-bit values in M1 to the 64-bit values in M2. */
> > #ifndef __SSE2__
> > #pragma GCC push_options
> > +#ifdef __x86_64__
> > +#pragma GCC target("sse2")
> > +#else
> > #pragma GCC target("sse2,mmx")
> > +#endif
> > #define __DISABLE_SSE2__
> > #endif /* __SSE2__ */
>
> Please also explain the need for the above changes.
>
These are needed to allow SSE emulation of MMX intrinsics. Without it,
I got
[hjl@gnu-cfl-1 gcc]$ cat
/export/gnu/import/git/gitlab/x86-gcc/gcc/testsuite/gcc.target/i386/sse2-mmx-4.c
/* { dg-do run { target { ! ia32 } } } */
/* { dg-options "-O2 -msse2 -mno-mmx" } */
#include "mmx-4.c"
[hjl@gnu-cfl-1 gcc]$ ./xgcc -B./ -S -O2 -msse2 -mno-mmx
/export/gnu/import/git/gitlab/x86-gcc/gcc/testsuite/gcc.target/i386/sse2-mmx-4.c
In file included from
/export/gnu/import/git/gitlab/x86-gcc/gcc/testsuite/gcc.target/i386/mmx-4.c:6,
from
/export/gnu/import/git/gitlab/x86-gcc/gcc/testsuite/gcc.target/i386/sse2-mmx-4.c:4:
/export/gnu/import/git/gitlab/x86-gcc/gcc/testsuite/gcc.target/i386/mmx-4.c:
In function ‘mmx_tests’:
./include/mmintrin.h:595:1: error: inlining failed in call to
always_inline ‘_mm_sll_si64’: target specific option mismatch
595 | _mm_sll_si64 (__m64 __m, __m64 __count)
| ^~~~~~~~~~~~
In file included from
/export/gnu/import/git/gitlab/x86-gcc/gcc/testsuite/gcc.target/i386/sse2-mmx-4.c:4:
/export/gnu/import/git/gitlab/x86-gcc/gcc/testsuite/gcc.target/i386/mmx-4.c:141:11:
note: called from here
141 | c64.v = _mm_sll_si64 (m64_64, s64);
| ^~~~~~~~~~~~~~~~~~~~~~~~~~
...
--
H.J.
