[committed, GCC-8, Arm] Backport of PR target/88224

[Andre Vieira (lists)]

Hi,

I committed a tweaked backport of 
https://gcc.gnu.org/ml/gcc-patches/2018-11/msg02276.html to the 
gcc-8-branch in r267124. There was a small subtle difference, since in 
GCC-8 we didn't enable fpu by default for cores, so rather than changing 
the default to use the right fpu, I changed the fpu option to the right 
configuration.

Cheers,
Andre


gcc/ChangeLog
2018-12-14  Andre Vieira  <andre.simoesdiasvie...@arm.com>

        Backport from mainline
        PR target/88224
        * config/arm/arm-cpus.in (armv7-r): Add FP16conv configurations.
        (cortex-r7, cortex-r8): Update fpu and add new configuration.
        * doc/invoke.texi (armv7-r): Add two new vfp options.
        (nofp.dp): Add cortex-r7 and cortex-r8 to the list of targets that
        support this option.
diff --git a/gcc/config/arm/arm-cpus.in b/gcc/config/arm/arm-cpus.in
index 
545321b0bbef10244b683d780d5b3d17b57077fb..8ba89ae48b9a63f389dba7481a8a27d99c8e6edf
 100644
--- a/gcc/config/arm/arm-cpus.in
+++ b/gcc/config/arm/arm-cpus.in
@@ -525,6 +525,8 @@ begin arch armv7-r
  optalias vfpv3xd fp.sp
  option fp add VFPv3 FP_DBL
  optalias vfpv3-d16 fp
+ option vfpv3xd-fp16 add VFPv3 fp16conv
+ option vfpv3-d16-fp16 add VFPv3 FP_DBL fp16conv
  option idiv add adiv
  option nofp remove ALL_FP
  option noidiv remove adiv
@@ -1335,7 +1337,8 @@ begin cpu cortex-r7
  cname cortexr7
  tune flags LDSCHED
  architecture armv7-r+idiv
- fpu vfpv3-d16
+ fpu vfpv3-d16-fp16
+ option nofp.dp remove FP_DBL
  option nofp remove ALL_FP
  costs cortex
 end cpu cortex-r7
@@ -1345,7 +1348,8 @@ begin cpu cortex-r8
  tune for cortex-r7
  tune flags LDSCHED
  architecture armv7-r+idiv
- fpu vfpv3-d16
+ fpu vfpv3-d16-fp16
+ option nofp.dp remove FP_DBL
  option nofp remove ALL_FP
  costs cortex
 end cpu cortex-r8
diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi
index 
3b42b7625ce6855711758f65352676bb02480d66..71523be76f2ff82143a70ddf6fdd7aec978f7e37
 100644
--- a/gcc/doc/invoke.texi
+++ b/gcc/doc/invoke.texi
@@ -16195,6 +16195,14 @@ The single-precision VFPv3 floating-point 
instructions.  The extension
 The VFPv3 floating-point instructions with 16 double-precision registers.
 The extension +vfpv3-d16 can be used as an alias for this extension.
 
+@item +vfpv3xd-d16-fp16
+The single-precision VFPv3 floating-point instructions with 16 double-precision
+registers and the half-precision floating-point conversion operations.
+
+@item +vfpv3-d16-fp16
+The VFPv3 floating-point instructions, with 16 double-precision
+registers and the half-precision floating-point conversion operations.
+
 @item +nofp
 Disable the floating-point extension.
 
@@ -16382,7 +16390,8 @@ Disables the floating-point and SIMD instructions on
 
 @item +nofp.dp
 Disables the double-precision component of the floating-point instructions
-on @samp{cortex-r5}, @samp{cortex-r52} and @samp{cortex-m7}.
+on @samp{cortex-r5}, @samp{cortex-r7}, @samp{cortex-r8}, @samp{cortex-r52} and
+@samp{cortex-m7}.
 
 @item +nosimd
 Disables the SIMD (but not floating-point) instructions on