On Wed, Aug 29, 2018 at 11:56 PM, Uros Bizjak <ubiz...@gmail.com> wrote: > On Thu, Aug 30, 2018 at 7:14 AM, Thiago Macieira > <thiago.macie...@intel.com> wrote: >> The instruction set first appeared with Westmere, but not all processors >> in that and the next few generations have the instructions. According to >> Wikipedia[1], the first generation in which all SKUs have AES >> instructions are Skylake and Goldmont. I can't find any Skylake, >> Kabylake, Kabylake-R or Cannon Lake currently listed at >> https://ark.intel.com that says "Intel® AES New Instructions" "No". >> >> [1] https://en.wikipedia.org/wiki/AES_instruction_set >> >> --- >> gcc/ >> >> 2018-08-27 Thiago Macieira <thiago.macie...@intel.com> >> >> config/i386/i386.c: Update PTA_WESTMERE, PTA_SKYLAKE >> and PTA_GOLDMONT > > LGTM, but let's wait for HJ's opinion. > > Thanks, > Uros. > >> --- >> gcc/config/i386/i386.c | 6 +++--- >> 1 file changed, 3 insertions(+), 3 deletions(-) >> >> diff --git a/gcc/config/i386/i386.c b/gcc/config/i386/i386.c >> index c437c18a29c..8672a666024 100644 >> --- a/gcc/config/i386/i386.c >> +++ b/gcc/config/i386/i386.c >> @@ -3479,7 +3479,7 @@ ix86_option_override_internal (bool main_args_p, >> | PTA_SSE3 | PTA_SSSE3 | PTA_CX16 | PTA_FXSR; >> const wide_int_bitmask PTA_NEHALEM = PTA_CORE2 | PTA_SSE4_1 | PTA_SSE4_2 >> | PTA_POPCNT; >> - const wide_int_bitmask PTA_WESTMERE = PTA_NEHALEM | PTA_AES | PTA_PCLMUL; >> + const wide_int_bitmask PTA_WESTMERE = PTA_NEHALEM | PTA_PCLMUL; >> const wide_int_bitmask PTA_SANDYBRIDGE = PTA_WESTMERE | PTA_AVX | >> PTA_XSAVE >> | PTA_XSAVEOPT; >> const wide_int_bitmask PTA_IVYBRIDGE = PTA_SANDYBRIDGE | PTA_FSGSBASE >> @@ -3488,7 +3488,7 @@ ix86_option_override_internal (bool main_args_p, >> | PTA_BMI2 | PTA_LZCNT | PTA_FMA | PTA_MOVBE | PTA_HLE; >> const wide_int_bitmask PTA_BROADWELL = PTA_HASWELL | PTA_ADX | PTA_PRFCHW >> | PTA_RDSEED; >> - const wide_int_bitmask PTA_SKYLAKE = PTA_BROADWELL | PTA_CLFLUSHOPT >> + const wide_int_bitmask PTA_SKYLAKE = PTA_BROADWELL | PTA_AES | >> PTA_CLFLUSHOPT >> | PTA_XSAVEC | PTA_XSAVES | PTA_SGX; >> const wide_int_bitmask PTA_SKYLAKE_AVX512 = PTA_SKYLAKE | PTA_AVX512F >> | PTA_AVX512CD | PTA_AVX512VL | PTA_AVX512BW | PTA_AVX512DQ | PTA_PKU >> @@ -3505,7 +3505,7 @@ ix86_option_override_internal (bool main_args_p, >> | PTA_AVX512F | PTA_AVX512CD; >> const wide_int_bitmask PTA_BONNELL = PTA_CORE2 | PTA_MOVBE; >> const wide_int_bitmask PTA_SILVERMONT = PTA_WESTMERE | PTA_MOVBE | >> PTA_RDRND; >> - const wide_int_bitmask PTA_GOLDMONT = PTA_SILVERMONT | PTA_SHA | PTA_XSAVE >> + const wide_int_bitmask PTA_GOLDMONT = PTA_SILVERMONT | PTA_AES | PTA_SHA >> | PTA_XSAVE >> | PTA_RDSEED | PTA_XSAVEC | PTA_XSAVES | PTA_CLFLUSHOPT | PTA_XSAVEOPT >> | PTA_FSGSBASE; >> const wide_int_bitmask PTA_GOLDMONT_PLUS = PTA_GOLDMONT | PTA_RDPID >> -- >> 2.18.0 >>
This is what I checked in. Thanks. -- H.J.
From 02b24aa8498cbdb26146092d05196a7e635a2302 Mon Sep 17 00:00:00 2001 From: "H.J. Lu" <hjl.to...@gmail.com> Date: Thu, 30 Aug 2018 08:57:46 -0700 Subject: [PATCH] x86: Move AESNI generation to Skylake and Goldmont MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The instruction set first appeared with Westmere, but not all processors in that and the next few generations have the instructions. According to Wikipedia[1], the first generation in which all SKUs have AES instructions are Skylake and Goldmont. I can't find any Skylake, Kabylake, Kabylake-R or Cannon Lake currently listed at https://ark.intel.com that says "Intel® AES New Instructions" "No". [1] https://en.wikipedia.org/wiki/AES_instruction_set 2018-08-30 Thiago Macieira <thiago.macie...@intel.com> * config/i386/i386.c (PTA_WESTMERE): Remove PTA_AES. (PTA_SKYLAKE): Add PTA_AES. (PTA_GOLDMONT): Likewise. --- gcc/ChangeLog | 6 ++++++ gcc/config/i386/i386.c | 6 +++--- 2 files changed, 9 insertions(+), 3 deletions(-) diff --git a/gcc/ChangeLog b/gcc/ChangeLog index fe6dacbc4dc..b0fa5ae9667 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,9 @@ +2018-08-30 Thiago Macieira <thiago.macie...@intel.com> + + * config/i386/i386.c (PTA_WESTMERE): Remove PTA_AES. + (PTA_SKYLAKE): Add PTA_AES. + (PTA_GOLDMONT): Likewise. + 2018-08-29 Jan Hubicka <j...@suse.cz> * lto-streamer-out.c (DFS::DFS_write_tree_body): Do not follow diff --git a/gcc/config/i386/i386.c b/gcc/config/i386/i386.c index c437c18a29c..8672a666024 100644 --- a/gcc/config/i386/i386.c +++ b/gcc/config/i386/i386.c @@ -3479,7 +3479,7 @@ ix86_option_override_internal (bool main_args_p, | PTA_SSE3 | PTA_SSSE3 | PTA_CX16 | PTA_FXSR; const wide_int_bitmask PTA_NEHALEM = PTA_CORE2 | PTA_SSE4_1 | PTA_SSE4_2 | PTA_POPCNT; - const wide_int_bitmask PTA_WESTMERE = PTA_NEHALEM | PTA_AES | PTA_PCLMUL; + const wide_int_bitmask PTA_WESTMERE = PTA_NEHALEM | PTA_PCLMUL; const wide_int_bitmask PTA_SANDYBRIDGE = PTA_WESTMERE | PTA_AVX | PTA_XSAVE | PTA_XSAVEOPT; const wide_int_bitmask PTA_IVYBRIDGE = PTA_SANDYBRIDGE | PTA_FSGSBASE @@ -3488,7 +3488,7 @@ ix86_option_override_internal (bool main_args_p, | PTA_BMI2 | PTA_LZCNT | PTA_FMA | PTA_MOVBE | PTA_HLE; const wide_int_bitmask PTA_BROADWELL = PTA_HASWELL | PTA_ADX | PTA_PRFCHW | PTA_RDSEED; - const wide_int_bitmask PTA_SKYLAKE = PTA_BROADWELL | PTA_CLFLUSHOPT + const wide_int_bitmask PTA_SKYLAKE = PTA_BROADWELL | PTA_AES | PTA_CLFLUSHOPT | PTA_XSAVEC | PTA_XSAVES | PTA_SGX; const wide_int_bitmask PTA_SKYLAKE_AVX512 = PTA_SKYLAKE | PTA_AVX512F | PTA_AVX512CD | PTA_AVX512VL | PTA_AVX512BW | PTA_AVX512DQ | PTA_PKU @@ -3505,7 +3505,7 @@ ix86_option_override_internal (bool main_args_p, | PTA_AVX512F | PTA_AVX512CD; const wide_int_bitmask PTA_BONNELL = PTA_CORE2 | PTA_MOVBE; const wide_int_bitmask PTA_SILVERMONT = PTA_WESTMERE | PTA_MOVBE | PTA_RDRND; - const wide_int_bitmask PTA_GOLDMONT = PTA_SILVERMONT | PTA_SHA | PTA_XSAVE + const wide_int_bitmask PTA_GOLDMONT = PTA_SILVERMONT | PTA_AES | PTA_SHA | PTA_XSAVE | PTA_RDSEED | PTA_XSAVEC | PTA_XSAVES | PTA_CLFLUSHOPT | PTA_XSAVEOPT | PTA_FSGSBASE; const wide_int_bitmask PTA_GOLDMONT_PLUS = PTA_GOLDMONT | PTA_RDPID -- 2.17.1
