GCC maintainers:
The following patch adds builtins to change the value of the FPSCR.
Specifically, __builtin_set_fpscr_rn, __builtin_set_fpscr_drn,
__builtin_mffsl, __builtin_mtfsb0, __builtin_mtfsb1. I added
documentation on the builtins in extend.texi. In addition to listing
the builtin, I added a C style comment to describe the builtin a
little. I don't see any of the other builtins documented like this.
But I felt some explanation of the builtins were helpful. Suggestions
on a better way to add the comments on the builtins would be
appreciated.
The patch has been tested on
powerpc64le-unknown-linux-gnu (Power 8 LE)
powerpc64le-unknown-linux-gnu (Power 9 LE)
With no regressions.
Please let me know if the patch looks OK for trunk.
Carl Love
---------------------------------------------------------
gcc/ChangeLog:
2018-08-16 Carl Love <c...@us.ibm.com>
* config/rs6000/rs6000-builtin.def: Add definitions for __builtin_mffsl,
__builtin_mtfsb0, __builtin_mtfsb1, __builtin_set_fpscr_rn,
__builtin_set_fpscr_drn.
* config/rs6000.c: Add functions rs6000_expand_mtfsb0_mtfsb1_builtin,
rs6000_expand_set_fpscr_rn_builtin, rs6000_expand_set_fpscr_drn_builtin.
Add case statement entries for the new builtins.
* config/rs6000.md: Add define_insn for rs6000_mtfsb0_si,
rs6000_mtfsb1_si, rs6000_mffscrn, rs6000_mffscdrn.
Add define_expand for rs6000_set_fpscr_rn and rs6000_set_fpscr_drn.
* doc/extend.texi: Add documentation for the builtins.
gcc/testsuite/ChangeLog:
2018-08-16 Carl Love <c...@us.ibm.com>
* testsuite/gcc.target/powerpc/test_mffsl-p9.c: New file.
* testsuite/gcc.target/powerpc/test_fpscr_builtins.c: New file.
* testsuite/gcc.target/powerpc/test_fpscr_builtins_error.c: New file.
---
gcc/config/rs6000/rs6000-builtin.def | 23 ++
gcc/config/rs6000/rs6000.c | 151 ++++++++++
gcc/config/rs6000/rs6000.md | 149 ++++++++-
gcc/doc/extend.texi | 20 ++
.../gcc.target/powerpc/test_fpscr_builtins.c | 282 ++++++++++++++++++
.../powerpc/test_fpscr_builtins_error.c | 26 ++
.../gcc.target/powerpc/test_mffsl-p9.c | 36 +++
7 files changed, 686 insertions(+), 1 deletion(-)
create mode 100644 gcc/testsuite/gcc.target/powerpc/test_fpscr_builtins.c
create mode 100644 gcc/testsuite/gcc.target/powerpc/test_fpscr_builtins_error.c
create mode 100644 gcc/testsuite/gcc.target/powerpc/test_mffsl-p9.c
diff --git a/gcc/config/rs6000/rs6000-builtin.def
b/gcc/config/rs6000/rs6000-builtin.def
index f79968154..a50236e77 100644
--- a/gcc/config/rs6000/rs6000-builtin.def
+++ b/gcc/config/rs6000/rs6000-builtin.def
@@ -2486,11 +2486,34 @@ BU_SPECIAL_X (RS6000_BUILTIN_MFTB, "__builtin_ppc_mftb",
BU_SPECIAL_X (RS6000_BUILTIN_MFFS, "__builtin_mffs",
RS6000_BTM_ALWAYS, RS6000_BTC_MISC)
+BU_SPECIAL_X (RS6000_BUILTIN_MFFSL, "__builtin_mffsl",
+ RS6000_BTM_ALWAYS, RS6000_BTC_MISC)
+
RS6000_BUILTIN_X (RS6000_BUILTIN_MTFSF, "__builtin_mtfsf",
RS6000_BTM_ALWAYS,
RS6000_BTC_MISC | RS6000_BTC_UNARY | RS6000_BTC_VOID,
CODE_FOR_rs6000_mtfsf)
+RS6000_BUILTIN_X (RS6000_BUILTIN_MTFSB0_SI, "__builtin_mtfsb0",
+ RS6000_BTM_ALWAYS,
+ RS6000_BTC_MISC | RS6000_BTC_UNARY,
+ CODE_FOR_rs6000_mtfsb0_si)
+
+RS6000_BUILTIN_X (RS6000_BUILTIN_MTFSB1_SI, "__builtin_mtfsb1",
+ RS6000_BTM_ALWAYS,
+ RS6000_BTC_MISC | RS6000_BTC_UNARY,
+ CODE_FOR_rs6000_mtfsb1_si)
+
+RS6000_BUILTIN_X (RS6000_BUILTIN_SET_FPSCR_RN, "__builtin_set_fpscr_rn",
+ RS6000_BTM_ALWAYS,
+ RS6000_BTC_MISC | RS6000_BTC_UNARY,
+ CODE_FOR_rs6000_set_fpscr_rn)
+
+RS6000_BUILTIN_X (RS6000_BUILTIN_SET_FPSCR_DRN, "__builtin_set_fpscr_drn",
+ RS6000_BTM_ALWAYS,
+ RS6000_BTC_MISC | RS6000_BTC_UNARY,
+ CODE_FOR_rs6000_set_fpscr_drn)
+
BU_SPECIAL_X (RS6000_BUILTIN_CPU_INIT, "__builtin_cpu_init",
RS6000_BTM_ALWAYS, RS6000_BTC_MISC)
diff --git a/gcc/config/rs6000/rs6000.c b/gcc/config/rs6000/rs6000.c
index aa707b255..7db9c10a9 100644
--- a/gcc/config/rs6000/rs6000.c
+++ b/gcc/config/rs6000/rs6000.c
@@ -13356,6 +13356,113 @@ rs6000_expand_mtfsf_builtin (enum insn_code icode,
tree exp)
return NULL_RTX;
}
+static rtx
+rs6000_expand_mtfsb0_mtfsb1_builtin (enum insn_code icode, tree exp)
+{
+ rtx pat;
+ tree arg0 = CALL_EXPR_ARG (exp, 0);
+ rtx op0 = expand_normal (arg0);
+ machine_mode mode0 = insn_data[icode].operand[0].mode;
+
+ if (icode == CODE_FOR_nothing)
+ /* Builtin not supported on this processor. */
+ return 0;
+
+ /* If we got invalid arguments bail out before generating bad rtl. */
+ if (arg0 == error_mark_node)
+ return const0_rtx;
+
+ /* Only allow bit numbers 0 to 31. */
+ if (GET_CODE (op0) != CONST_INT || INTVAL (op0) < 0 || INTVAL (op0) > 31)
+ {
+ error ("Argument must be a constant between 0 and 31.");
+ return const0_rtx;
+ }
+
+ if (! (*insn_data[icode].operand[0].predicate) (op0, mode0))
+ op0 = copy_to_mode_reg (mode0, op0);
+
+ pat = GEN_FCN (icode) (op0);
+ if (! pat)
+ return const0_rtx;
+ emit_insn (pat);
+
+ return NULL_RTX;
+}
+
+static rtx
+rs6000_expand_set_fpscr_rn_builtin (enum insn_code icode, tree exp)
+{
+ rtx pat;
+ tree arg0 = CALL_EXPR_ARG (exp, 0);
+ rtx op0 = expand_normal (arg0);
+ machine_mode mode0 = insn_data[icode].operand[0].mode;
+
+ if (icode == CODE_FOR_nothing)
+ /* Builtin not supported on this processor. */
+ return 0;
+
+ /* If we got invalid arguments bail out before generating bad rtl. */
+ if (arg0 == error_mark_node)
+ return const0_rtx;
+
+ /* If the argument is a constant, check the range. Agrument can only be a
+ 2-bit value. Unfortunately, can't check the range of the value at
+ compile time if the argument is a variable.
+ */
+ if (GET_CODE (op0) == CONST_INT && (INTVAL (op0) < 0 || INTVAL (op0) > 3))
+ {
+ error ("Argument must be a value between 0 and 3.");
+ return const0_rtx;
+ }
+
+ if (! (*insn_data[icode].operand[0].predicate) (op0, mode0))
+ op0 = copy_to_mode_reg (mode0, op0);
+
+ pat = GEN_FCN (icode) (op0);
+ if (! pat)
+ return const0_rtx;
+ emit_insn (pat);
+
+ return NULL_RTX;
+}
+static rtx
+rs6000_expand_set_fpscr_drn_builtin (enum insn_code icode, tree exp)
+{
+ rtx pat;
+ tree arg0 = CALL_EXPR_ARG (exp, 0);
+ rtx op0 = expand_normal (arg0);
+ machine_mode mode0 = insn_data[icode].operand[0].mode;
+
+ if (icode == CODE_FOR_nothing)
+ /* Builtin not supported on this processor. */
+ return 0;
+
+ /* If we got invalid arguments bail out before generating bad rtl. */
+ if (arg0 == error_mark_node)
+ return const0_rtx;
+
+ /* If the argument is a constant, check the range. Agrument can only be a
+ 3-bit value. Unfortunately, can't check the range of the value at
+ compile time if the argument is a variable.
+ */
+ if (GET_CODE (op0) == CONST_INT && (INTVAL (op0) < 0 || INTVAL (op0) > 7))
+ {
+ error ("Argument must be a value between 0 and 7.");
+ return const0_rtx;
+ }
+
+ if (! (*insn_data[icode].operand[0].predicate) (op0, mode0))
+ op0 = copy_to_mode_reg (mode0, op0);
+
+ pat = GEN_FCN (icode) (op0);
+ if (! pat)
+ return const0_rtx;
+ emit_insn (pat);
+
+ return NULL_RTX;
+}
+
static rtx
rs6000_expand_unop_builtin (enum insn_code icode, tree exp, rtx target)
{
@@ -15987,6 +16094,26 @@ rs6000_expand_builtin (tree exp, rtx target, rtx
subtarget ATTRIBUTE_UNUSED,
case RS6000_BUILTIN_MFFS:
return rs6000_expand_zeroop_builtin (CODE_FOR_rs6000_mffs, target);
+ case RS6000_BUILTIN_MTFSB0_SI:
+ return rs6000_expand_mtfsb0_mtfsb1_builtin (CODE_FOR_rs6000_mtfsb0_si,
+ exp);
+
+ case RS6000_BUILTIN_MTFSB1_SI:
+ return rs6000_expand_mtfsb0_mtfsb1_builtin (CODE_FOR_rs6000_mtfsb1_si,
+ exp);
+
+ case RS6000_BUILTIN_SET_FPSCR_RN:
+ return rs6000_expand_set_fpscr_rn_builtin (CODE_FOR_rs6000_set_fpscr_rn,
+ exp);
+
+ case RS6000_BUILTIN_SET_FPSCR_DRN:
+ return
+ rs6000_expand_set_fpscr_drn_builtin (CODE_FOR_rs6000_set_fpscr_drn,
+ exp);
+
+ case RS6000_BUILTIN_MFFSL:
+ return rs6000_expand_zeroop_builtin (CODE_FOR_rs6000_mffsl, target);
+
case RS6000_BUILTIN_MTFSF:
return rs6000_expand_mtfsf_builtin (CODE_FOR_rs6000_mtfsf, exp);
@@ -16370,6 +16497,30 @@ rs6000_init_builtins (void)
ftype = build_function_type_list (double_type_node, NULL_TREE);
def_builtin ("__builtin_mffs", ftype, RS6000_BUILTIN_MFFS);
+ ftype = build_function_type_list (double_type_node, NULL_TREE);
+ def_builtin ("__builtin_mffsl", ftype, RS6000_BUILTIN_MFFSL);
+
+ ftype = build_function_type_list (void_type_node,
+ intSI_type_node,
+ NULL_TREE);
+
+ def_builtin ("__builtin_mtfsb0", ftype, RS6000_BUILTIN_MTFSB0_SI);
+
+ ftype = build_function_type_list (void_type_node,
+ intSI_type_node,
+ NULL_TREE);
+ def_builtin ("__builtin_mtfsb1", ftype, RS6000_BUILTIN_MTFSB1_SI);
+
+ ftype = build_function_type_list (void_type_node,
+ intDI_type_node,
+ NULL_TREE);
+ def_builtin ("__builtin_set_fpscr_rn", ftype, RS6000_BUILTIN_SET_FPSCR_RN);
+
+ ftype = build_function_type_list (void_type_node,
+ intDI_type_node,
+ NULL_TREE);
+ def_builtin ("__builtin_set_fpscr_drn", ftype, RS6000_BUILTIN_SET_FPSCR_DRN);
+
ftype = build_function_type_list (void_type_node,
intSI_type_node, double_type_node,
NULL_TREE);
diff --git a/gcc/config/rs6000/rs6000.md b/gcc/config/rs6000/rs6000.md
index d70b01b8c..7714aacd8 100644
--- a/gcc/config/rs6000/rs6000.md
+++ b/gcc/config/rs6000/rs6000.md
@@ -163,7 +163,13 @@
UNSPECV_MFTB ; move from time base
UNSPECV_NLGR ; non-local goto receiver
UNSPECV_MFFS ; Move from FPSCR
- UNSPECV_MTFSF ; Move to FPSCR Fields
+ UNSPECV_MFFSL ; Move from FPSCR light instruction version
+ UNSPECV_MFFSCRN ; Move from FPSCR float rounding mode
+ UNSPECV_MFFSCDRN ; Move from FPSCR decimal float rounding mode
+ UNSPECV_MTFSF ; Move to FPSCR Fields 8 to 15
+ UNSPECV_MTFSF_L0W1 ; Move to FPSCR Fields 0 to 7
+ UNSPECV_MTFSFB0 ; Set FPSCR Field bit to 0
+ UNSPECV_MTFSFB1 ; Set FPSCR Field bit to 1
UNSPECV_SPLIT_STACK_RETURN ; A camouflaged return
UNSPECV_SPEC_BARRIER ; Speculation barrier
])
@@ -5823,6 +5829,115 @@
xscvdpuxds %x0,%x1"
[(set_attr "type" "fp")])
+(define_insn "rs6000_mtfsb0_si"
+ [(use (match_operand:SI 0 "short_cint_operand" "n"))
+ (unspec_volatile:SI [(const_int 0)] UNSPECV_MTFSFB0)]
+ "TARGET_HARD_FLOAT"
+ "mtfsb0 %0")
+
+(define_insn "rs6000_mtfsb1_si"
+ [(use (match_operand:SI 0 "short_cint_operand" "n"))
+ (unspec_volatile:SI [(const_int 0)] UNSPECV_MTFSFB1)]
+ "TARGET_HARD_FLOAT"
+ "mtfsb1 %0")
+
+(define_insn "rs6000_mffscrn"
+ [(set (match_operand:DF 0 "gpc_reg_operand" "=d")
+ (unspec_volatile:DF [(const_int 0)] UNSPECV_MFFSCRN))
+ (use (match_operand:DF 1 "gpc_reg_operand" "d"))]
+ "TARGET_HARD_FLOAT"
+ "mffscrn %0,%1")
+
+(define_insn "rs6000_mffscdrn"
+ [(set (match_operand:DF 0 "gpc_reg_operand" "=d")
+ (unspec_volatile:DF [(const_int 0)] UNSPECV_MFFSCDRN))
+ (use (match_operand:DF 1 "gpc_reg_operand" "d"))]
+ "TARGET_HARD_FLOAT"
+ "mffscdrn %0,%1")
+
+(define_expand "rs6000_set_fpscr_rn"
+ [(match_operand:DI 0 "gpc_reg_operand")]
+ "TARGET_HARD_FLOAT"
+{
+ rtx tmp_df = gen_reg_rtx (DFmode);
+
+ /* The floating point rounding control bits are FPSCR[62:63]. Put the
+ new rounding mode bits from operands[0][62:63] into FPSCR[62:63]. */
+ if (TARGET_P9_VECTOR)
+ {
+ rtx src_df = gen_reg_rtx (DImode);
+
+ src_df = simplify_gen_subreg (DFmode, operands[0], DImode, 0);
+ emit_insn (gen_rs6000_mffscrn (tmp_df, src_df));
+ }
+ else
+ {
+ rtx tmp_rn = gen_reg_rtx (DImode);
+ rtx tmp_di = gen_reg_rtx (DImode);
+
+ /* Extract new RN mode from operand. */
+ emit_insn (gen_anddi3_mask (tmp_rn, operands[0], GEN_INT (0x3)));
+
+ /* Insert new RN mode into FSCPR. */
+ emit_insn (gen_rs6000_mffs (tmp_df));
+ tmp_di = simplify_gen_subreg (DImode, tmp_df, DFmode, 0);
+ emit_insn (gen_anddi3_mask (tmp_di, tmp_di, GEN_INT (0xFFFFFFFC)));
+ emit_insn (gen_iordi3 (tmp_di, tmp_di, tmp_rn));
+
+ /* Need to write to field k=15. The fields are [0:15]. Hence with L=0,
+ W=0, FLM_i must be equal to 8, 16 = i + 8*(1-W). FLM is an 8 bit
+ field[0:7]. Need to set the bit that corresponds to the value of i
+ that you want [0:7].
+ */
+ tmp_df = simplify_gen_subreg (DFmode, tmp_di, DImode, 0);
+ emit_insn (gen_rs6000_mtfsf (GEN_INT (0x01), tmp_df));
+ }
+ DONE;
+})
+
+(define_expand "rs6000_set_fpscr_drn"
+ [(match_operand:DI 0 "gpc_reg_operand")]
+ "TARGET_HARD_FLOAT"
+{
+ rtx tmp_df = gen_reg_rtx (DFmode);
+
+ /* The decimal floating point rounding control bits are FPSCR[29:31]. Put the
+ new rounding mode bits from operands[0][61:63] into FPSCR[29:31]. */
+
+ if (TARGET_P9_VECTOR)
+ {
+ rtx src_df = gen_reg_rtx (DFmode);
+
+ emit_insn (gen_ashldi3 (operands[0], operands[0], GEN_INT (32)));
+ src_df = simplify_gen_subreg (DFmode, operands[0], DImode, 0);
+ emit_insn (gen_rs6000_mffscdrn (tmp_df, src_df));
+ }
+ else
+ {
+ rtx tmp_rn = gen_reg_rtx (DImode);
+ rtx tmp_di = gen_reg_rtx (DImode);
+
+ /* Extract new DRN mode from operand. */
+ emit_insn (gen_anddi3_mask (tmp_rn, operands[0], GEN_INT (0x7)));
+ emit_insn (gen_ashldi3 (tmp_rn, tmp_rn, GEN_INT (32)));
+
+ /* Insert new RN mode into FSCPR. */
+ emit_insn (gen_rs6000_mffs (tmp_df));
+ tmp_di = simplify_gen_subreg (DImode, tmp_df, DFmode, 0);
+ emit_insn (gen_anddi3_mask (tmp_di, tmp_di, GEN_INT (0xFFF8FFFFFFFF)));
+ emit_insn (gen_iordi3 (tmp_di, tmp_di, tmp_rn));
+
+ /* Need to write to field k=7. The fields are [0:15]. Hence with L=0,
+ W=1, FLM_i must be equal to 7, 16 = i + 8*(1-W). FLM is an 8 bit
+ field[0:7]. Need to set the bit that corresponds to the value of i
+ that you want [0:7].
+ */
+ tmp_df = simplify_gen_subreg (DFmode, tmp_di, DImode, 0);
+ emit_insn (gen_rs6000_mtfsf_L0W1 (GEN_INT (0x01), tmp_df));
+ }
+ DONE;
+})
+
;; Here, we use (set (reg) (unspec:DI [(fix:SI ...)] UNSPEC_FCTIWZ))
;; rather than (set (subreg:SI (reg)) (fix:SI ...))
;; because the first makes it clear that operand 0 is not live
@@ -13602,6 +13717,31 @@
})
+;; The ISA 3.0 mffsl instruction is a lower latency instruction
+;; for reading the FPSCR
+(define_insn "rs6000_mffsl0"
+ [(set (match_operand:DF 0 "gpc_reg_operand" "=d")
+ (unspec_volatile:DF [(const_int 0)] UNSPECV_MFFSL))]
+ "TARGET_HARD_FLOAT && TARGET_P9_MISC"
+ "mffsl %0")
+
+(define_expand "rs6000_mffsl"
+ [(set (match_operand:DF 0 "gpc_reg_operand")
+ (unspec_volatile:DF [(const_int 0)] UNSPECV_MFFSL))]
+ "TARGET_HARD_FLOAT && TARGET_P9_MISC"
+{
+ /* If the low latency mffsl instruction (ISA 3.0) is available use it,
+ otherwise fall back to the older mffs instruction which does the same
+ thing but with a little more latency. */
+
+ if (TARGET_P9_VECTOR)
+ emit_insn (gen_rs6000_mffsl0 (operands[0]));
+ else
+ emit_insn (gen_rs6000_mffs (operands[0]));
+
+ DONE;
+})
+
(define_insn "rs6000_mffs"
[(set (match_operand:DF 0 "gpc_reg_operand" "=d")
(unspec_volatile:DF [(const_int 0)] UNSPECV_MFFS))]
@@ -13615,6 +13755,13 @@
"TARGET_HARD_FLOAT"
"mtfsf %0,%1")
+(define_insn "rs6000_mtfsf_L0W1"
+ [(unspec_volatile [(match_operand:SI 0 "const_int_operand" "i")
+ (match_operand:DF 1 "gpc_reg_operand" "d")]
+ UNSPECV_MTFSF_L0W1)]
+ "TARGET_HARD_FLOAT"
+ "mtfsf %0,%1,0,1")
+
;; Power8 fusion support for fusing an addis instruction with a D-form load of
;; a GPR. The addis instruction must be adjacent to the load, and use the same
diff --git a/gcc/doc/extend.texi b/gcc/doc/extend.texi
index 130f6a671..7c6279ec2 100644
--- a/gcc/doc/extend.texi
+++ b/gcc/doc/extend.texi
@@ -15745,6 +15745,16 @@ uint64_t __builtin_ppc_get_timebase ();
unsigned long __builtin_ppc_mftb ();
__ibm128 __builtin_unpack_ibm128 (__ibm128, int);
__ibm128 __builtin_pack_ibm128 (double, double);
+double __builtin_mffs(void); /* Return value of the FPSCR register.
+ Note, ISA 3.0 supports __builtin_mffsl()
+ which is a lower latency version of this
+ builtin. */
+void __builtin_mtfsb0(const int); /* Argument can be 0 to 31. Sets
+ the specified bit in the FPSCR to 0. */
+void __builtin_mtfsb1(const int); /* Argument can be 0 to 31. Sets
+ the specified bit in the FPSCR to 1. */
+void __builtin_set_fpscr_rn(int); /* The argument is a the 2-bit value to set
+ the Floating point rounding mode to. */
@end smallexample
The @code{__builtin_ppc_get_timebase} and @code{__builtin_ppc_mftb}
@@ -15803,6 +15813,10 @@ long long __builtin_dxex (_Decimal64);
long long __builtin_dxexq (_Decimal128);
_Decimal128 __builtin_pack_dec128 (unsigned long long, unsigned long long);
unsigned long long __builtin_unpack_dec128 (_Decimal128, int);
+void __builtin_set_fpscr_drn(int); /* The argument is a the 3-bit value to
+ set the Decimal Floating point rounding
+ mode to. */
+
@end smallexample
The following functions require @option{-mhard-float},
@@ -16004,6 +16018,12 @@ int __builtin_dfp_dtstsfi_ov (unsigned int comparison,
_Decimal64 value);
int __builtin_dfp_dtstsfi_ov (unsigned int comparison, _Decimal128 value);
int __builtin_dfp_dtstsfi_ov_dd (unsigned int comparison, _Decimal64 value);
int __builtin_dfp_dtstsfi_ov_td (unsigned int comparison, _Decimal128 value);
+
+double __builtin_mffsl(void); /* Return value of the FPSCR register. Uses
+ lower latency version of the mffs
+ instruction. Defaults to mffs for pre
+ ISA 3.0. */
+
@end smallexample
The @code{__builtin_byte_in_set} function requires a
64-bit environment supporting ISA 3.0 or later. This function returns
diff --git a/gcc/testsuite/gcc.target/powerpc/test_fpscr_builtins.c
b/gcc/testsuite/gcc.target/powerpc/test_fpscr_builtins.c
new file mode 100644
index 000000000..4f77078c6
--- /dev/null
+++ b/gcc/testsuite/gcc.target/powerpc/test_fpscr_builtins.c
@@ -0,0 +1,282 @@
+/* { dg-do run { target { powerpc64*-*-* && lp64 } } } */
+/* { dg-require-effective-target lp64 } */
+/* { dg-options "-pedantic" } */
+
+#include <altivec.h>
+
+#define DEBUG 1
+
+#ifdef DEBUG
+#include <stdio.h>
+#endif
+
+#define RN_MASK 0x3LL /* RN field mask */
+#define DRN_MASK 0x700000000LL /* DRN field mask */
+
+void abort (void);
+
+int main ()
+{
+ int i;
+ int val, bit;
+ double fpscr_val;
+ union blah {
+ double d;
+ unsigned long long ll;
+ } conv_val;
+
+ unsigned long long ll_value;
+ register double f14;
+
+ /* __builtin_set_fpscr_rn() builtin can take a const or a variable
+ value between 0 and 3 as the argument.
+ __builtin_set_fpscr_drn() builtin can take a const or a variable
+ value between 0 and 7 as the argument.
+ __builtin_mtfsb0 and __builtin_mtfsb1 argument must be a constant
+ 30 or 31.
+ */
+
+ /* Test reading the FPSCR register */
+ asm volatile ("mffs %0" : "=f"(f14));
+ conv_val.d = f14;
+
+ if (conv_val.d != __builtin_mffs())
+ {
+#ifdef DEBUG
+ printf("ERROR, __builtin_mffs() returned 0x%llx, not the expecected
value 0x%llx\n",
+ __builtin_mffs(), conv_val.d);
+#else
+ abort();
+#endif
+ }
+
+ /* Test float rounding mode builtin with const value argument. */
+ __builtin_set_fpscr_rn(3);
+ conv_val.d = __builtin_mffs();
+ ll_value = conv_val.ll & RN_MASK;
+
+ if (ll_value != 3)
+ {
+#ifdef DEBUG
+ printf("ERROR, __builtin_set_fpscr_rn(3) returned 0x%llx, not the
expecected value 0x%x\n",
+ ll_value, 3);
+#else
+ abort();
+#endif
+ }
+
+ val = 2;
+ __builtin_set_fpscr_rn(val);
+ conv_val.d = __builtin_mffs();
+ ll_value = conv_val.ll & RN_MASK;
+
+ if (ll_value != val)
+ {
+#ifdef DEBUG
+ printf("ERROR, __builtin_set_fpscr_rn(val=%d) returned 0x%llx, not the
expecected value 0x%x\n",
+ val, ll_value, val);
+#else
+ abort();
+#endif
+ }
+
+ /* Reset to 0 for testing */
+ val = 0;
+ __builtin_set_fpscr_rn(val);
+
+ __builtin_mtfsb1(31);
+ conv_val.d = __builtin_mffs();
+ ll_value = conv_val.ll & 0x1LL;
+
+ if (ll_value != 1)
+ {
+#ifdef DEBUG
+ printf("ERROR, __builtin_mtfsb1(31) did not set the bit to a 1.\n");
+#else
+ abort();
+#endif
+ }
+
+ __builtin_mtfsb0(31);
+ conv_val.d = __builtin_mffs();
+ ll_value = conv_val.ll & 0x1LL;
+
+ if (ll_value != 0)
+ {
+#ifdef DEBUG
+ printf("ERROR, __builtin_mtfsb0(31) did not set the bit to a 0.\n");
+#else
+ abort();
+#endif
+ }
+
+ __builtin_mtfsb1(30);
+ conv_val.d = __builtin_mffs();
+ ll_value = conv_val.ll & 0x2LL;
+
+ if (ll_value != 2)
+ {
+#ifdef DEBUG
+ printf("ERROR, __builtin_mtfsb1(31) did not set the bit to a 1.\n");
+#else
+ abort();
+#endif
+ }
+
+ __builtin_mtfsb0(30);
+ conv_val.d = __builtin_mffs();
+ ll_value = conv_val.ll & 0x2LL;
+
+ if (ll_value != 0)
+ {
+#ifdef DEBUG
+ printf("ERROR, __builtin_mtfsb1(31) did not set the bit to a 0.\n");
+#else
+ abort();
+#endif
+ }
+
+ __builtin_mtfsb1(0);
+ conv_val.d = __builtin_mffs();
+ ll_value = conv_val.ll & (0x1LL << (31-0));
+
+ if (ll_value != (0x1LL << (31-0)))
+ {
+#ifdef DEBUG
+ printf("ERROR, __builtin_mtfsb1(0) did not set the bit to a 1.\n");
+#else
+ abort();
+#endif
+ }
+
+ __builtin_mtfsb0(0);
+ conv_val.d = __builtin_mffs();
+ ll_value = conv_val.ll & (0x1LL << (31-0));
+
+ if (ll_value != 0)
+ {
+#ifdef DEBUG
+ printf("ERROR, __builtin_mtfsb0(0) did not set the bit to a 0.\n");
+#else
+ abort();
+#endif
+ }
+
+
+ /* Test builtin float rounding mode with variable as argument. */
+ val = 0;
+ __builtin_set_fpscr_rn(val);
+ conv_val.d = __builtin_mffs();
+ ll_value = conv_val.ll & RN_MASK;
+
+ if (ll_value != val)
+ {
+#ifdef DEBUG
+ printf("ERROR, __builtin_set_fpscr_rn(val=%d) did not set rounding mode
to %x.\n",
+ val, val);
+#else
+ abort();
+#endif
+ }
+
+ val = 3;
+ __builtin_set_fpscr_rn(val);
+ conv_val.d = __builtin_mffs();
+ ll_value = conv_val.ll & RN_MASK;
+
+ if (ll_value != val)
+ {
+#ifdef DEBUG
+ printf("ERROR, __builtin_set_fpscr_rn(val=%d) did not set rounding mode
to %x.\n",
+ val, val);
+#else
+ abort();
+#endif
+ }
+
+ /* Test builtin decimal float rounding mode with const argument. */
+ __builtin_set_fpscr_drn(7);
+ conv_val.d = __builtin_mffs();
+ ll_value = conv_val.ll & DRN_MASK;
+
+ if (ll_value != 0x700000000)
+ {
+#ifdef DEBUG
+ printf("ERROR, __builtin_set_fpscr_drn(7) did not set rounding mode
to 7.\n");
+#else
+ abort();
+#endif
+ }
+
+ __builtin_set_fpscr_drn(2);
+ conv_val.d = __builtin_mffs();
+ ll_value = conv_val.ll & DRN_MASK;
+
+ if (ll_value != 0x200000000)
+ {
+#ifdef DEBUG
+ printf("ERROR, __builtin_set_fpscr_drn(2) did not set rounding mode
to 2.\n");
+#else
+ abort();
+#endif
+ }
+
+ __builtin_set_fpscr_drn(5);
+ conv_val.d = __builtin_mffs();
+ ll_value = conv_val.ll & DRN_MASK;
+
+ if (ll_value != 0x500000000)
+ {
+#ifdef DEBUG
+ printf("ERROR, __builtin_set_fpscr_drn(5) did not set rounding mode
to 5.\n");
+#else
+ abort();
+#endif
+ }
+
+ /* Test builtin decimal float rounding mode with variable as argument. */
+ val = 7;
+ __builtin_set_fpscr_drn(val);
+ conv_val.d = __builtin_mffs();
+ ll_value = conv_val.ll & DRN_MASK;
+
+ if (ll_value != ((unsigned long long)val << 32))
+ {
+#ifdef DEBUG
+ printf("ERROR, __builtin_set_fpscr_drn(val=%d) did not set rounding
mode to %d.\n",
+ val, val);
+#else
+ abort();
+#endif
+ }
+
+ val = 0;
+ __builtin_set_fpscr_drn(val);
+ conv_val.d = __builtin_mffs();
+ ll_value = conv_val.ll & DRN_MASK;
+
+ if (ll_value != ((unsigned long long)val << 32))
+ {
+#ifdef DEBUG
+ printf("ERROR, __builtin_set_fpscr_drn(val=%d) did not set rounding
mode to %d.\n",
+ val, val);
+#else
+ abort();
+#endif
+ }
+
+ val = 2;
+ __builtin_set_fpscr_drn(val);
+ conv_val.d = __builtin_mffs();
+ ll_value = conv_val.ll & DRN_MASK;
+
+ if (ll_value != ((unsigned long long)val << 32))
+ {
+#ifdef DEBUG
+ printf("ERROR, __builtin_set_fpscr_drn(val=%d) did not set rounding
mode to %d.\n",
+ val, val);
+#else
+ abort();
+#endif
+ }
+}
diff --git a/gcc/testsuite/gcc.target/powerpc/test_fpscr_builtins_error.c
b/gcc/testsuite/gcc.target/powerpc/test_fpscr_builtins_error.c
new file mode 100644
index 000000000..10de0be44
--- /dev/null
+++ b/gcc/testsuite/gcc.target/powerpc/test_fpscr_builtins_error.c
@@ -0,0 +1,26 @@
+/* { dg-do compile { target powerpc*-*-* } } */
+
+#include <altivec.h>
+
+int main ()
+{
+
+ /* Test builin with out of range arguments. Can only test for constant
+ int arguments. The builtins __builtin_set_fpscr_rn(),
+ __builtin_set_fpscr_drn() also support a variable as an argument but
+ can't test variable value at compile time. */
+
+ __builtin_mtfsb0(-1); /* { dg-error "Argument must be a constant between 0
and 31." } */
+ __builtin_mtfsb0(32); /* { dg-error "Argument must be a constant between 0
and 31." } */
+
+ __builtin_mtfsb1(-1); /* { dg-error "Argument must be a constant between 0
and 31." } */
+ __builtin_mtfsb1(32); /* { dg-error "Argument must be a constant between 0
and 31." } */
+
+ __builtin_set_fpscr_rn(-1); /* { dg-error "Argument must be a value between
0 and 3." } */
+ __builtin_set_fpscr_rn(4); /* { dg-error "Argument must be a value between
0 and 3." } */
+
+ __builtin_set_fpscr_drn(-1); /* { dg-error "Argument must be a value
between 0 and 7." } */
+ __builtin_set_fpscr_drn(8); /* { dg-error "Argument must be a value
between 0 and 7." } */
+
+}
+
diff --git a/gcc/testsuite/gcc.target/powerpc/test_mffsl-p9.c
b/gcc/testsuite/gcc.target/powerpc/test_mffsl-p9.c
new file mode 100644
index 000000000..dc4f863ca
--- /dev/null
+++ b/gcc/testsuite/gcc.target/powerpc/test_mffsl-p9.c
@@ -0,0 +1,36 @@
+/* { dg-do run { target { powerpc*-*-linux* && { lp64 && p9vector_hw } } } } */
+/* { dg-require-effective-target powerpc_p9vector_ok } */
+/* { dg-options "-pedantic -mcpu=power9" } */
+/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } {
"-mcpu=power9" } } */
+
+#include <altivec.h>
+
+#ifdef DEBUG
+#include <stdio.h>
+#endif
+
+void abort (void);
+
+int main ()
+{
+
+ register double f14;
+ union blah {
+ double d;
+ unsigned long long ll;
+ } conv_val;
+
+ /* Test reading the FPSCR register. */
+ asm volatile ("mffs %0" : "=f"(f14));
+ conv_val.d = f14;
+
+ if (conv_val.d != __builtin_mffsl())
+ {
+#ifdef DEBUG
+ printf("ERROR, __builtin_mffsl() returned 0x%llx, not the expecected
value 0x%llx\n",
+ __builtin_mffsl(), conv_val.d);
+#else
+ abort();
+#endif
+ }
+}
--
2.17.1
