> On 26 Jul 2018, at 10:13, Alan Hayward <alan.hayw...@arm.com> wrote: > > This is rebasing of the patch posted in November. > It's aim is to support aarch64 SVE register preservation around TLS calls > by adding a CLOBBER_HIGH expression. > > Across a TLS call, Aarch64 SVE does not explicitly preserve the > SVE vector registers. However, the Neon vector registers are preserved. > Due to overlapping of registers, this means the lower 128bits of all > SVE vector registers will be preserved. > > The existing GCC code assume all Neon and SVE registers are clobbered > across TLS calls. > > This patch introduces a CLOBBER_HIGH expression. This behaves a bit like > a CLOBBER expression. CLOBBER_HIGH can only refer to a single register. > The mode of the expression indicates the size of the lower bits which > will be preserved. If the register contains a value bigger than this > mode then the code will treat the register as clobbered, otherwise the > register remains untouched. > > The means in order to evaluate if a clobber high is relevant, we need to > ensure the mode of the existing value in a register is tracked. > > The first two patches introduce CLOBBER_HIGH and generation support. > The next patch adds a helper function for easily determining if a register > gets clobbered by a CLOBBER_HIGH. > The next three patches add clobber high checks to all of the passes. I > couldn't think of a better way of splitting this up (maybe needs dividing > into smaller patches?). > Finally the last patch adds the CLOBBER_HIGHS around a TLS call for > aarch64 SVE and some test cases. > > Alan Hayward (7): > Add CLOBBER_HIGH expression > Generation support for CLOBBER_HIGH > Add func to check if register is clobbered by clobber_high > lra support for clobber_high > cse support for clobber_high > Remaining support for clobber high > Enable clobber high for tls descs on Aarch64 > > gcc/alias.c | 11 ++ > gcc/cfgexpand.c | 1 + > gcc/combine-stack-adj.c | 1 + > gcc/combine.c | 38 ++++- > gcc/config/aarch64/aarch64.md | 69 ++++++-- > gcc/cse.c | 187 ++++++++++++++------- > gcc/cselib.c | 42 +++-- > gcc/cselib.h | 2 +- > gcc/dce.c | 11 +- > gcc/df-scan.c | 6 + > gcc/doc/rtl.texi | 15 +- > gcc/dwarf2out.c | 1 + > gcc/emit-rtl.c | 16 ++ > gcc/genconfig.c | 1 + > gcc/genemit.c | 51 +++--- > gcc/genrecog.c | 3 +- > gcc/haifa-sched.c | 3 + > gcc/ira-build.c | 5 + > gcc/ira-costs.c | 7 + > gcc/ira.c | 6 +- > gcc/jump.c | 1 + > gcc/lra-eliminations.c | 11 ++ > gcc/lra-int.h | 2 + > gcc/lra-lives.c | 31 ++-- > gcc/lra.c | 66 +++++--- > gcc/postreload-gcse.c | 21 ++- > gcc/postreload.c | 25 ++- > gcc/print-rtl.c | 1 + > gcc/recog.c | 9 +- > gcc/regcprop.c | 10 +- > gcc/reginfo.c | 4 + > gcc/reload1.c | 16 +- > gcc/reorg.c | 27 ++- > gcc/resource.c | 24 ++- > gcc/rtl.c | 15 ++ > gcc/rtl.def | 10 ++ > gcc/rtl.h | 27 ++- > gcc/rtlanal.c | 47 +++++- > gcc/sched-deps.c | 15 +- > .../gcc.target/aarch64/sve_tls_preserve_1.c | 19 +++ > .../gcc.target/aarch64/sve_tls_preserve_2.c | 24 +++ > .../gcc.target/aarch64/sve_tls_preserve_3.c | 24 +++ > 42 files changed, 725 insertions(+), 180 deletions(-) > create mode 100644 gcc/testsuite/gcc.target/aarch64/sve_tls_preserve_1.c > create mode 100644 gcc/testsuite/gcc.target/aarch64/sve_tls_preserve_2.c > create mode 100644 gcc/testsuite/gcc.target/aarch64/sve_tls_preserve_3.c > > -- > 2.15.2 (Apple Git-101.1) >
