Hi!
While testing other patches also with -masm=intel, I've noticed that
several insns output wrong mem sizes. The following patch fixes what I
found. %w1/%k1/%q1 will still %xmmN if it is a register and for AT&T
syntax will print memory as normally, but for -masm=intel it will
print WORD PTR/DWORD PTR/QWORD PTR instead of always XMMWORD PTR.
The changes are to insns that read fewer than 16 bytes from memory
and just extend it somehow into the whole %xmm resp. %ymm register.
Bootstrapped/regtested on x86_64-linux and i686-linux, ok for trunk?
2011-10-27 Jakub Jelinek <ja...@redhat.com>
* config/i386/i386.c (ix86_print_operand): Handle 'q' and 'x'
overrides for -masm=intel memory.
* config/i386/sse.md (sse2_cvtdq2pd, sse2_cvtps2pd,
sse4_1_<code>v8qiv8hi2, avx2_<code>v8qiv8si2,
sse4_1_<code>v4hiv4si2, avx2_<code>v4hiv4di2,
sse4_1_<code>v2siv2di2): Use %q1 instead of %1 for -masm=intel.
(sse4_1_<code>v4qiv4si2, avx2_<code>v4qiv4di2,
sse4_1_<code>v2hiv2di2): Use %k1 instead of %1 for -masm=intel.
(sse4_1_<code>v2qiv2di2): Use %w1 instead of %1 for -masm=intel.
--- gcc/config/i386/i386.c.jj 2011-10-27 08:42:51.000000000 +0200
+++ gcc/config/i386/i386.c 2011-10-27 18:14:48.000000000 +0200
@@ -14118,13 +14118,18 @@ ix86_print_operand (FILE *file, rtx x, i
gcc_unreachable ();
}
- /* Check for explicit size override (codes 'b', 'w' and 'k') */
+ /* Check for explicit size override (codes 'b', 'w', 'k',
+ 'q' and 'x') */
if (code == 'b')
size = "BYTE";
else if (code == 'w')
size = "WORD";
else if (code == 'k')
size = "DWORD";
+ else if (code == 'q')
+ size = "QWORD";
+ else if (code == 'x')
+ size = "XMMWORD";
fputs (size, file);
fputs (" PTR ", file);
--- gcc/config/i386/sse.md.jj 2011-10-27 18:26:28.000000000 +0200
+++ gcc/config/i386/sse.md 2011-10-27 18:23:52.000000000 +0200
@@ -2529,7 +2530,7 @@ (define_insn "sse2_cvtdq2pd"
(match_operand:V4SI 1 "nonimmediate_operand" "xm")
(parallel [(const_int 0) (const_int 1)]))))]
"TARGET_SSE2"
- "%vcvtdq2pd\t{%1, %0|%0, %1}"
+ "%vcvtdq2pd\t{%1, %0|%0, %q1}"
[(set_attr "type" "ssecvt")
(set_attr "prefix" "maybe_vex")
(set_attr "mode" "V2DF")])
@@ -2764,7 +2765,7 @@ (define_insn "sse2_cvtps2pd"
(match_operand:V4SF 1 "nonimmediate_operand" "xm")
(parallel [(const_int 0) (const_int 1)]))))]
"TARGET_SSE2"
- "%vcvtps2pd\t{%1, %0|%0, %1}"
+ "%vcvtps2pd\t{%1, %0|%0, %q1}"
[(set_attr "type" "ssecvt")
(set_attr "amdfam10_decode" "direct")
(set_attr "athlon_decode" "double")
@@ -9750,7 +9751,7 @@ (define_insn "sse4_1_<code>v8qiv8hi2"
(const_int 6)
(const_int 7)]))))]
"TARGET_SSE4_1"
- "%vpmov<extsuffix>bw\t{%1, %0|%0, %1}"
+ "%vpmov<extsuffix>bw\t{%1, %0|%0, %q1}"
[(set_attr "type" "ssemov")
(set_attr "prefix_extra" "1")
(set_attr "prefix" "maybe_vex")
@@ -9770,7 +9771,7 @@ (define_insn "avx2_<code>v8qiv8si2"
(const_int 6)
(const_int 7)]))))]
"TARGET_AVX2"
- "vpmov<extsuffix>bd\t{%1, %0|%0, %1}"
+ "vpmov<extsuffix>bd\t{%1, %0|%0, %q1}"
[(set_attr "type" "ssemov")
(set_attr "prefix_extra" "1")
(set_attr "prefix" "vex")
@@ -9786,7 +9787,7 @@ (define_insn "sse4_1_<code>v4qiv4si2"
(const_int 2)
(const_int 3)]))))]
"TARGET_SSE4_1"
- "%vpmov<extsuffix>bd\t{%1, %0|%0, %1}"
+ "%vpmov<extsuffix>bd\t{%1, %0|%0, %k1}"
[(set_attr "type" "ssemov")
(set_attr "prefix_extra" "1")
(set_attr "prefix" "maybe_vex")
@@ -9813,7 +9814,7 @@ (define_insn "sse4_1_<code>v4hiv4si2"
(const_int 2)
(const_int 3)]))))]
"TARGET_SSE4_1"
- "%vpmov<extsuffix>wd\t{%1, %0|%0, %1}"
+ "%vpmov<extsuffix>wd\t{%1, %0|%0, %q1}"
[(set_attr "type" "ssemov")
(set_attr "prefix_extra" "1")
(set_attr "prefix" "maybe_vex")
@@ -9829,7 +9830,7 @@ (define_insn "avx2_<code>v4qiv4di2"
(const_int 2)
(const_int 3)]))))]
"TARGET_AVX2"
- "vpmov<extsuffix>bq\t{%1, %0|%0, %1}"
+ "vpmov<extsuffix>bq\t{%1, %0|%0, %k1}"
[(set_attr "type" "ssemov")
(set_attr "prefix_extra" "1")
(set_attr "prefix" "vex")
@@ -9843,7 +9844,7 @@ (define_insn "sse4_1_<code>v2qiv2di2"
(parallel [(const_int 0)
(const_int 1)]))))]
"TARGET_SSE4_1"
- "%vpmov<extsuffix>bq\t{%1, %0|%0, %1}"
+ "%vpmov<extsuffix>bq\t{%1, %0|%0, %w1}"
[(set_attr "type" "ssemov")
(set_attr "prefix_extra" "1")
(set_attr "prefix" "maybe_vex")
@@ -9859,7 +9860,7 @@ (define_insn "avx2_<code>v4hiv4di2"
(const_int 2)
(const_int 3)]))))]
"TARGET_AVX2"
- "vpmov<extsuffix>wq\t{%1, %0|%0, %1}"
+ "vpmov<extsuffix>wq\t{%1, %0|%0, %q1}"
[(set_attr "type" "ssemov")
(set_attr "prefix_extra" "1")
(set_attr "prefix" "vex")
@@ -9873,7 +9874,7 @@ (define_insn "sse4_1_<code>v2hiv2di2"
(parallel [(const_int 0)
(const_int 1)]))))]
"TARGET_SSE4_1"
- "%vpmov<extsuffix>wq\t{%1, %0|%0, %1}"
+ "%vpmov<extsuffix>wq\t{%1, %0|%0, %k1}"
[(set_attr "type" "ssemov")
(set_attr "prefix_extra" "1")
(set_attr "prefix" "maybe_vex")
@@ -9897,7 +9898,7 @@ (define_insn "sse4_1_<code>v2siv2di2"
(parallel [(const_int 0)
(const_int 1)]))))]
"TARGET_SSE4_1"
- "%vpmov<extsuffix>dq\t{%1, %0|%0, %1}"
+ "%vpmov<extsuffix>dq\t{%1, %0|%0, %q1}"
[(set_attr "type" "ssemov")
(set_attr "prefix_extra" "1")
(set_attr "prefix" "maybe_vex")
Jakub
