On Tue, May 22, 2018 at 08:13:22AM -0500, Kyrill Tkachov wrote:
> [sending on behalf of Jackson Woodruff]
>
> Hi all,
>
> This patch merges loads and stores from D-registers that are of different
> modes.
>
> Code like this:
>
> typedef int __attribute__((vector_size(8))) vec;
> struct pair
> {
> vec v;
> double d;
> }
>
> Now generates a store pair instruction:
>
> void
> assign (struct pair *p, vec v)
> {
> p->v = v;
> p->d = 1.0;
> }
>
> Whereas previously it generated two `str` instructions.
>
> This patch also merges storing of double zero values with
> long integer values:
>
> struct pair
> {
> long long l;
> double d;
> }
>
> void
> foo (struct pair *p)
> {
> p->l = 10;
> p->d = 0.0;
> }
>
> Now generates a single store pair instruction rather than two `str`
> instructions.
>
> The patch basically generalises the mode iterators on the patterns in
> aarch64.md
> and the peepholes in aarch64-ldpstp.md to take all combinations of pairs of
> modes
> so, while it may be a large-ish patch, it does fairly mechanical stuff.
>
> Bootstrap and testsuite run OK. OK for trunk?
OK for trunk.
Thanks,
James
>
> Jackson
>
> 2018-05-22 Jackson Woodruff <[email protected]>
> Kyrylo Tkachov <[email protected]>
>
> * config/aarch64/aarch64.md: New patterns to generate stp
> and ldp.
> (store_pair_sw, store_pair_dw): New patterns to generate stp for
> single words and double words.
> (load_pair_sw, load_pair_dw): Likewise.
> (store_pair_sf, store_pair_df, store_pair_si, store_pair_di):
> Delete.
> (load_pair_sf, load_pair_df, load_pair_si, load_pair_di):
> Delete.
> * config/aarch64/aarch64-ldpstp.md: Modify peephole
> for different mode ldpstp and add peephole for merged zero stores.
> Likewise for loads.
> * config/aarch64/aarch64.c (aarch64_operands_ok_for_ldpstp):
> Add size check.
> (aarch64_gen_store_pair): Rename calls to match new patterns.
> (aarch64_gen_load_pair): Rename calls to match new patterns.
> * config/aarch64/aarch64-simd.md (load_pair<mode>): Rename to...
> (load_pair<DREG:mode><DREG2:mode>): ... This.
> (store_pair<mode>): Rename to...
> (vec_store_pair<DREG:mode><DREG2:mode>): ... This.
> * config/aarch64/iterators.md (DREG, DREG2, DX2, SX, SX2, DSX):
> New mode iterators.
> (V_INT_EQUIV): Handle SImode.
> * config/aarch64/predicates.md (aarch64_reg_zero_or_fp_zero):
> New predicate.
>
>
> 2018-05-22 Jackson Woodruff <[email protected]>
>
> * gcc.target/aarch64/ldp_stp_6.c: New.
> * gcc.target/aarch64/ldp_stp_7.c: New.
> * gcc.target/aarch64/ldp_stp_8.c: New.
