GCC Maintainers:
I updated the patch so the dcbtt and dctstt instructions are only
generated if the supported ISA is 2.06 or newer. I addressed the use
of REG instead of REG_P and formatting issues as requested.
The regression testing of the patch was done on
powerpc64le-unknown-linux-gnu (Power 8 LE)
with no regressions.
Additional manual testing to verify the correct instruction generation
was don on Power 8 LE. The results are:
gcc -g -c prefetch.c
objdump -S -d prefetch.o | more
...
/* data prefetch , instructions hit the cache. */
__builtin_prefetch (&data[0], 0, 0);
c: 2c 00 3f 39 addi r9,r31,44
10: 2c 4a 00 7e dcbtt 0,r9
__builtin_prefetch (&data[0], 0, 1);
14: 2c 00 3f 39 addi r9,r31,44
18: 2c 4a 00 7c dcbt 0,r9
__builtin_prefetch (&data[0], 0, 2);
1c: 2c 00 3f 39 addi r9,r31,44
20: 2c 4a 00 7c dcbt 0,r9
__builtin_prefetch (&data[0], 0, 3);
24: 2c 00 3f 39 addi r9,r31,44
28: 2c 4a 00 7c dcbt 0,r9
__builtin_prefetch (&data[0], 1, 0);
2c: 2c 00 3f 39 addi r9,r31,44
30: ec 49 00 7e dcbtstt 0,r9
__builtin_prefetch (&data[0], 1, 1);
34: 2c 00 3f 39 addi r9,r31,44
38: ec 49 00 7c dcbtst 0,r9
__builtin_prefetch (&data[0], 1, 2);
3c: 2c 00 3f 39 addi r9,r31,44
40: ec 49 00 7c dcbtst 0,r9
__builtin_prefetch (&data[0], 1, 3);
44: 2c 00 3f 39 addi r9,r31,44
48: ec 49 00 7c dcbtst 0,r9
Please let me know if the patch looks OK for GCC mainline.
Carl Love
------------------------------------------------
test case gcc/testsuite/gcc.target/sh/prefetch.c
gcc/ChangeLog:
2018-05-10 Carl Love <c...@us.ibm.com>
* config/rs6000/rs6000.md (prefetch): Generate dcbtt and dcbtstt
instructions if operands[2] is 0.
---
gcc/config/rs6000/rs6000.md | 20 +++++++++++++++++---
1 file changed, 17 insertions(+), 3 deletions(-)
diff --git a/gcc/config/rs6000/rs6000.md b/gcc/config/rs6000/rs6000.md
index 2b15cca..8536c89 100644
--- a/gcc/config/rs6000/rs6000.md
+++ b/gcc/config/rs6000/rs6000.md
@@ -13233,9 +13233,23 @@
(match_operand:SI 2 "const_int_operand" "n"))]
""
{
- if (GET_CODE (operands[0]) == REG)
- return INTVAL (operands[1]) ? "dcbtst 0,%0" : "dcbt 0,%0";
- return INTVAL (operands[1]) ? "dcbtst %a0" : "dcbt %a0";
+ /* dcbtstt, dcbtt and TM=0b10000 support starts with ISA 2.06. */
+ int inst_select = INTVAL (operands[2]) || !TARGET_POPCNTD;
+
+ if (REG_P (operands[0]))
+ {
+ if (INTVAL (operands[1]) == 0)
+ return inst_select ? "dcbt 0,%0" : "dcbtt 0,%0";
+ else
+ return inst_select ? "dcbtst 0,%0" : "dcbtstt 0,%0";
+ }
+ else
+ {
+ if (INTVAL (operands[1]) == 0)
+ return inst_select ? "dcbt %a0" : "dcbtt %a0";
+ else
+ return inst_select ? "dcbtst %a0" : "dcbtstt %a0";
+ }
}
[(set_attr "type" "load")])
--
2.7.4
