On Tue, Apr 24, 2018 at 04:38:31PM +0100, Kyrill Tkachov wrote: > Hi all, > > In this testcase it is possible to generate an invalid SISD shift of zero: > Error: immediate value out of range 1 to 64 at operand 3 -- `sshr > v9.2s,v0.2s,0' > > The SSHR and USHR instructions require a shift from 1 up to the element size. > However our constraints on the scalar shifts that generate these patterns > allow a shift amount of zero as well. The pure GP-reg ASR and LSR > instructions allow a shift amount of zero. > > It is unlikely that a shift of zero will survive till the end of compilation, > but it's not impossible, as this PR shows. > > The patch tightens up the constraints in the offending patterns by adding two > new constraints that allow shift amounts [1,32] and [1,64] and using them in > *aarch64_ashr_sisd_or_int_<mode>3 > and *aarch64_lshr_sisd_or_int_<mode>3. > The left-shift SISD instructions SHL and USHL allow a shift amount of zero so > don't need adjustment The vector shift patterns that map down to SSHR and > USHR already enforce the correct immediate range. > > Bootstrapped and tested on aarch64-none-linux-gnu. > Ok for trunk?
OK if the release managers are fine with this. I was a little nervous that we were tightening restrictions on an instruction which has caused trouble in the past, but this patch looks right to me. Thanks, James > 2018-04-24 Kyrylo Tkachov <kyrylo.tkac...@arm.com> > > PR target/85512 > * config/aarch64/constraints.md (Usg, Usj): New constraints. > * config/aarch64/iterators.md (cmode_simd): New mode attribute. > * config/aarch64/aarch64.md (*aarch64_ashr_sisd_or_int_<mode>3): > Use the above on operand 2. Reindent. > (*aarch64_lshr_sisd_or_int_<mode>3): Likewise. > > 2018-04-24 Kyrylo Tkachov <kyrylo.tkac...@arm.com> > > PR target/85512 > * gcc.dg/pr85512.c: New test.
