On Wed, Oct 19, 2011 at 6:21 AM, Uros Bizjak <ubiz...@gmail.com> wrote:
> On Wed, Oct 19, 2011 at 3:07 PM, Kirill Yukhin <kirill.yuk...@gmail.com>
> wrote:
>
>> Here is (almost obvous) patch, which fixes PR50766.
>>
>> ChangeLog entry:
>> 2011-10-19 Kirill Yukhin <kirill.yuk...@intel.com>
>>
>> * config/i386/i386.md (bmi_bextr_<mode>): Update register/
>> memory operand order.
>> (bmi2_bzhi_<mode>3): Ditto.
>> (bmi2_pdep_<mode>3): Ditto.
>> (bmi2_pext_<mode>3): Ditto.
Please mention PR #.
>> Bootstrapped, test (from bug) passing.
>>
>> Could you please have a look?
>
> Please also add the testcase from the PR. You can use { dg-do
> assemble }, but you have to check for BMI2 effective target support.
>
> BTW: I can't find BMI2 instruction reference documentation, so I'm
It is in Intel AVX spec:
http://software.intel.com/en-us/avx/
> just rubberstamping the patch as obvious.
>
--
H.J.
