On 25 January 2018 at 11:24, Richard Sandiford
<richard.sandif...@linaro.org> wrote:
> Rainer Orth <r...@cebitec.uni-bielefeld.de> writes:
>> Jeff Law <l...@redhat.com> writes:
>>> On 11/22/2017 11:12 AM, Richard Sandiford wrote:
>>>> Richard Sandiford <richard.sandif...@linaro.org> writes:
>>>>> This patch adds support for the SVE bitwise reduction instructions
>>>>> (ANDV, ORV and EORV). It's a fairly mechanical extension of existing
>>>>> REDUC_* operators.
>>>>>
>>>>> Tested on aarch64-linux-gnu (with and without SVE), x86_64-linux-gnu
>>>>> and powerpc64le-linux-gnu.
>>>>
>>>> Here's an updated version that applies on top of the recent
>>>> removal of REDUC_*_EXPR. Tested as before.
>>>>
>>>> Thanks,
>>>> Richard
>>>>
>>>>
>>>> 2017-11-22 Richard Sandiford <richard.sandif...@linaro.org>
>>>> Alan Hayward <alan.hayw...@arm.com>
>>>> David Sherwood <david.sherw...@arm.com>
>>>>
>>>> gcc/
>>>> * optabs.def (reduc_and_scal_optab, reduc_ior_scal_optab)
>>>> (reduc_xor_scal_optab): New optabs.
>>>> * doc/md.texi (reduc_and_scal_@var{m}, reduc_ior_scal_@var{m})
>>>> (reduc_xor_scal_@var{m}): Document.
>>>> * doc/sourcebuild.texi (vect_logical_reduc): Likewise.
>>>> * internal-fn.def (IFN_REDUC_AND, IFN_REDUC_IOR, IFN_REDUC_XOR): New
>>>> internal functions.
>>>> * fold-const-call.c (fold_const_call): Handle them.
>>>> * tree-vect-loop.c (reduction_fn_for_scalar_code): Return the new
>>>> internal functions for BIT_AND_EXPR, BIT_IOR_EXPR and BIT_XOR_EXPR.
>>>> * config/aarch64/aarch64-sve.md (reduc_<bit_reduc>_scal_<mode>):
>>>> (*reduc_<bit_reduc>_scal_<mode>): New patterns.
>>>> * config/aarch64/iterators.md (UNSPEC_ANDV, UNSPEC_ORV)
>>>> (UNSPEC_XORV): New unspecs.
>>>> (optab): Add entries for them.
>>>> (BITWISEV): New int iterator.
>>>> (bit_reduc_op): New int attributes.
>>>>
>>>> gcc/testsuite/
>>>> * lib/target-supports.exp (check_effective_target_vect_logical_reduc):
>>>> New proc.
>>>> * gcc.dg/vect/vect-reduc-or_1.c: Also run for vect_logical_reduc
>>>> and add an associated scan-dump test. Prevent vectorization
>>>> of the first two loops.
>>>> * gcc.dg/vect/vect-reduc-or_2.c: Likewise.
>>>> * gcc.target/aarch64/sve_reduc_1.c: Add AND, IOR and XOR reductions.
>>>> * gcc.target/aarch64/sve_reduc_2.c: Likewise.
>>>> * gcc.target/aarch64/sve_reduc_1_run.c: Likewise.
>>>> (INIT_VECTOR): Tweak initial value so that some bits are always set.
>>>> * gcc.target/aarch64/sve_reduc_2_run.c: Likewise.
>>> OK.
>>> Jeff
>>
>> Two tests have regressed on sparc-sun-solaris2.*:
>>
>> +FAIL: gcc.dg/vect/vect-reduc-or_1.c -flto -ffat-lto-objects
>> scan-tree-dump vect "Reduce using vector shifts"
>> +FAIL: gcc.dg/vect/vect-reduc-or_1.c scan-tree-dump vect "Reduce using
>> vector shifts"
>> +FAIL: gcc.dg/vect/vect-reduc-or_2.c -flto -ffat-lto-objects
>> scan-tree-dump vect "Reduce using vector shifts"
>> +FAIL: gcc.dg/vect/vect-reduc-or_2.c scan-tree-dump vect "Reduce using
>> vector shifts"
>
> Bah, I think I broke this yesterday in:
>
> 2018-01-24 Richard Sandiford <richard.sandif...@linaro.org>
>
> PR testsuite/83889
> [...]
> * gcc.dg/vect/vect-reduc-or_1.c: Remove conditional dg-do run.
> * gcc.dg/vect/vect-reduc-or_2.c: Likewise.
>
> (r257022), which removed:
>
> /* { dg-do run { target { whole_vector_shift || vect_logical_reduc } } } */
>
> I'd somehow thought that the dump lines in these two tests were already
> guarded, but they weren't.
>
> Tested on aarch64-linux-gnu and x86_64-linux-gnu and applied as obvious.
> Sorry for the breakage.
>
> Richard
>
>
Hi Richard,
While this fixes the regression on armeb (same as on sparc), the
effect on arm-none-linux-gnueabi and arm-none-eabi
is that the tests are now skipped, while they used to pass.
Is this expected? Or is the guard you added too restrictive?
Thanks,
Christophe
> 2018-01-25 Richard Sandiford <richard.sandif...@linaro.org>
>
> gcc/testsuite/
> * gcc.dg/vect/vect-reduc-or_1.c: Require whole_vector_shift for
> the shift dump line.
> * gcc.dg/vect/vect-reduc-or_2.c: Likewise.
>
> Index: gcc/testsuite/gcc.dg/vect/vect-reduc-or_1.c
> ===================================================================
> --- gcc/testsuite/gcc.dg/vect/vect-reduc-or_1.c 2018-01-24 16:22:31.724089913
> +0000
> +++ gcc/testsuite/gcc.dg/vect/vect-reduc-or_1.c 2018-01-25 10:16:16.283500281
> +0000
> @@ -45,5 +45,5 @@ main (unsigned char argc, char **argv)
> return 0;
> }
>
> -/* { dg-final { scan-tree-dump "Reduce using vector shifts" "vect" { target
> { ! vect_logical_reduc } } } } */
> +/* { dg-final { scan-tree-dump "Reduce using vector shifts" "vect" { target
> { whole_vector_shift && { ! vect_logical_reduc } } } } } */
> /* { dg-final { scan-tree-dump "Reduce using direct vector reduction" "vect"
> { target vect_logical_reduc } } } */
> Index: gcc/testsuite/gcc.dg/vect/vect-reduc-or_2.c
> ===================================================================
> --- gcc/testsuite/gcc.dg/vect/vect-reduc-or_2.c 2018-01-24 16:22:31.724089913
> +0000
> +++ gcc/testsuite/gcc.dg/vect/vect-reduc-or_2.c 2018-01-25 10:16:16.284500239
> +0000
> @@ -44,5 +44,5 @@ main (unsigned char argc, char **argv)
> return 0;
> }
>
> -/* { dg-final { scan-tree-dump "Reduce using vector shifts" "vect" { target
> { ! vect_logical_reduc } } } } */
> +/* { dg-final { scan-tree-dump "Reduce using vector shifts" "vect" { target
> { whole_vector_shift && { ! vect_logical_reduc } } } } } */
> /* { dg-final { scan-tree-dump "Reduce using direct vector reduction" "vect"
> { target vect_logical_reduc } } } */
