On Fri, Nov 24, 2017 at 03:59:58PM +0000, Richard Sandiford wrote: > Richard Sandiford <richard.sandif...@linaro.org> writes: > > This series adds support for ARM's Scalable Vector Extension. > > More details on SVE can be found here: > > > > > > https://developer.arm.com/products/architecture/a-profile/docs/arm-architecture-reference-manual-supplement-armv8-a > > > > There are four parts for ease of review, but it probably makes > > sense to commit them as one patch. > > > > The series plugs SVE into the current vectorisation framework without > > adding any new features to the framework itself. This means for example > > that vector loops still handle full vectors, with a scalar epilogue loop > > being needed for the rest. Later patches add support for other features > > like fully-predicated loops. > > > > The patches build on top of the various series that I've already posted. > > Sorry that there were so many, and thanks again for all the reviews. > > > > Tested on aarch64-linux-gnu without SVE and aarch64-linux-gnu with SVE > > (in the default vector-length agnostic mode). Also tested with > > -msve-vector-bits=256 and -msve-vector-bits=512 to select 256-bit > > and 512-bit SVE registers. > > Here's an update based on an off-list discussion with the maintainers. > Changes since v1: > > - Changed the names of the modes from 256-bit vectors to "VNx" > + a 128-bit mode name, e.g. V32QI -> VNx16QI. > > - Added an "sve" attribute and used it in the "enabled" attribute. > This allows generic aarch64.md patterns to disable things related > to SVE on non-SVE targets; previously this was implicit through the > constraints. > > - Improved the consistency of the constraint names, specifically: > > Ua?: addition contraints (already used for Uaa) > Us?: general scalar constraints (already used for various other scalars) > Ut?: memory constraints (unchanged from v1) > vs?: vector SVE constraints (mostly unchanged, but now includes FP > as well as integer constraints) > > There's still the general "Dm" (minus one) constraint, for consistency > with "Dz" (zero). > > - Added missing register descriptions above FIXED_REGISTERS. > > - "should"/"is expected to" -> "must". > > - Added more commentary to things like regmode_natural_size. > > I also did a before and after comparison of the testsuite output > for base AArch64 (but using the new FIRST_PSEUDO_REGISTER definition > to avoid changes to hash values). There were no differences.
I seem to have lost 4/4 in my mailer. Would you mind pinging it if I have any action to take? Also, please ping any other SVE parts I've missed that you haven't pinged in recent days. I'll get to 1/4 in good time, but at 5000+ lines, it will need at least another day! I'd like to OK everything around it which is outstanding, then build up the courage for the big patch! Thanks, James
