Hi,
this patch updates tuning flags for generic. It drops flags used by old
chips (X86_TUNE_PARTIAL_FLAG_REG_STALL which is needed only for original
core2, X86_TUNE_PAD_RETURNS which is needed for pre-buldozer chips)
and enables fussion logic because it seems wasteful to let scheduler
prevent it.
I will upate scheduler model incrementally.
Bootstrapped/regtested x86_64-linux, plan commit it today.
Honza
* x86-tune.def (X86_TUNE_PARTIAL_FLAG_REG_STALL): Disable for
generic
(X86_TUNE_FUSE_CMP_AND_BRANCH_32, X86_TUNE_FUSE_CMP_AND_BRANCH_64,
X86_TUNE_FUSE_CMP_AND_BRANCH_SOFLAGS, X86_TUNE_FUSE_ALU_AND_BRANCH):
Enable for generic.
(X86_TUNE_PAD_RETURNS): Disable for generic.
Index: i386/x86-tune.def
===================================================================
--- i386/x86-tune.def (revision 255304)
+++ i386/x86-tune.def (working copy)
@@ -75,12 +75,10 @@ DEF_TUNE (X86_TUNE_SSE_SPLIT_REGS, "sse_
setting full flags.
The flags does not affect generation of INC and DEC that is controlled
- by X86_TUNE_USE_INCDEC.
+ by X86_TUNE_USE_INCDEC. */
- This flag may be dropped from generic once core2-corei5 machines are
- rare enough. */
DEF_TUNE (X86_TUNE_PARTIAL_FLAG_REG_STALL, "partial_flag_reg_stall",
- m_CORE2 | m_GENERIC)
+ m_CORE2)
/* X86_TUNE_MOVX: Enable to zero extend integer registers to avoid
partial dependencies. */
@@ -99,25 +97,25 @@ DEF_TUNE (X86_TUNE_MEMORY_MISMATCH_STALL
conditional jump instruction for 32 bit TARGET.
FIXME: revisit for generic. */
DEF_TUNE (X86_TUNE_FUSE_CMP_AND_BRANCH_32, "fuse_cmp_and_branch_32",
- m_CORE_ALL | m_BDVER | m_ZNVER1)
+ m_CORE_ALL | m_BDVER | m_ZNVER1 | m_GENERIC)
/* X86_TUNE_FUSE_CMP_AND_BRANCH_64: Fuse compare with a subsequent
conditional jump instruction for TARGET_64BIT.
FIXME: revisit for generic. */
DEF_TUNE (X86_TUNE_FUSE_CMP_AND_BRANCH_64, "fuse_cmp_and_branch_64",
- m_NEHALEM | m_SANDYBRIDGE | m_HASWELL | m_BDVER | m_ZNVER1)
+ m_NEHALEM | m_SANDYBRIDGE | m_HASWELL | m_BDVER | m_ZNVER1 |
m_GENERIC)
/* X86_TUNE_FUSE_CMP_AND_BRANCH_SOFLAGS: Fuse compare with a
subsequent conditional jump instruction when the condition jump
check sign flag (SF) or overflow flag (OF). */
DEF_TUNE (X86_TUNE_FUSE_CMP_AND_BRANCH_SOFLAGS, "fuse_cmp_and_branch_soflags",
- m_NEHALEM | m_SANDYBRIDGE | m_HASWELL | m_BDVER | m_ZNVER1)
+ m_NEHALEM | m_SANDYBRIDGE | m_HASWELL | m_BDVER | m_ZNVER1 |
m_GENERIC)
/* X86_TUNE_FUSE_ALU_AND_BRANCH: Fuse alu with a subsequent conditional
jump instruction when the alu instruction produces the CCFLAG consumed by
the conditional jump instruction. */
DEF_TUNE (X86_TUNE_FUSE_ALU_AND_BRANCH, "fuse_alu_and_branch",
- m_SANDYBRIDGE | m_HASWELL)
+ m_SANDYBRIDGE | m_HASWELL | m_GENERIC)
/*****************************************************************************/
@@ -194,7 +192,7 @@ DEF_TUNE (X86_TUNE_PAD_SHORT_FUNCTION, "
architecture expect at most one jump per 2 byte window. Failing to
pad returns leads to misaligned return stack. */
DEF_TUNE (X86_TUNE_PAD_RETURNS, "pad_returns",
- m_ATHLON_K8 | m_AMDFAM10 | m_GENERIC)
+ m_ATHLON_K8 | m_AMDFAM10)
/* X86_TUNE_FOUR_JUMP_LIMIT: Some CPU cores are not able to predict more
than 4 branch instructions in the 16 byte window. */
