diff --git a/gcc/config/aarch64/aarch64.md b/gcc/config/aarch64/aarch64.md index 389f2f9..c466c94 100644 --- a/gcc/config/aarch64/aarch64.md +++ b/gcc/config/aarch64/aarch64.md @@ -1651,25 +1651,123 @@ } ) +(define_expand "addv4" + [(match_operand:GPI 0 "register_operand") + (match_operand:GPI 1 "register_operand") + (match_operand:GPI 2 "register_operand") + (match_operand 3 "")] + "" +{ + emit_insn (gen_add3_compareV (operands[0], operands[1], operands[2])); + aarch64_gen_unlikely_cbranch (NE, CC_Vmode, operands[3]); + + DONE; +}) + +(define_expand "uaddv4" + [(match_operand:GPI 0 "register_operand") + (match_operand:GPI 1 "register_operand") + (match_operand:GPI 2 "register_operand") + (match_operand 3 "")] + "" +{ + emit_insn (gen_add3_compareC (operands[0], operands[1], operands[2])); + aarch64_gen_unlikely_cbranch (NE, CC_Cmode, operands[3]); + + DONE; +}) + + (define_expand "addti3" [(set (match_operand:TI 0 "register_operand" "") (plus:TI (match_operand:TI 1 "register_operand" "") - (match_operand:TI 2 "register_operand" "")))] + (match_operand:TI 2 "aarch64_reg_or_imm" "")))] "" { - rtx low = gen_reg_rtx (DImode); - emit_insn (gen_adddi3_compareC (low, gen_lowpart (DImode, operands[1]), - gen_lowpart (DImode, operands[2]))); + rtx l0,l1,l2,h0,h1,h2; - rtx high = gen_reg_rtx (DImode); - emit_insn (gen_adddi3_carryin (high, gen_highpart (DImode, operands[1]), - gen_highpart (DImode, operands[2]))); + aarch64_add_128bit_scratch_regs (operands[1], operands[2], + &l0, &l1, &l2, &h0, &h1, &h2); + + if (l2 == const0_rtx) + { + l0 = l1; + if (!aarch64_pluslong_operand (h2, DImode)) + h2 = force_reg (DImode, h2); + emit_insn (gen_adddi3 (h0, h1, h2)); + } + else + { + emit_insn (gen_adddi3_compareC (l0, l1, force_reg (DImode, l2))); + emit_insn (gen_adddi3_carryin (h0, h1, force_reg (DImode, h2))); + } + + emit_move_insn (gen_lowpart (DImode, operands[0]), l0); + emit_move_insn (gen_highpart (DImode, operands[0]), h0); - emit_move_insn (gen_lowpart (DImode, operands[0]), low); - emit_move_insn (gen_highpart (DImode, operands[0]), high); DONE; }) +(define_expand "addvti4" + [(match_operand:TI 0 "register_operand" "") + (match_operand:TI 1 "register_operand" "") + (match_operand:TI 2 "aarch64_reg_or_imm" "") + (match_operand 3 "")] + "" +{ + rtx l0,l1,l2,h0,h1,h2; + + aarch64_add_128bit_scratch_regs (operands[1], operands[2], + &l0, &l1, &l2, &h0, &h1, &h2); + + if (l2 == const0_rtx) + { + l0 = l1; + emit_insn (gen_adddi3_compareV (h0, h1, force_reg (DImode, h2))); + } + else + { + emit_insn (gen_adddi3_compareC (l0, l1, force_reg (DImode, l2))); + emit_insn (gen_adddi3_carryinV (h0, h1, force_reg (DImode, h2))); + } + + emit_move_insn (gen_lowpart (DImode, operands[0]), l0); + emit_move_insn (gen_highpart (DImode, operands[0]), h0); + + aarch64_gen_unlikely_cbranch (NE, CC_Vmode, operands[3]); + DONE; +}) + +(define_expand "uaddvti4" + [(match_operand:TI 0 "register_operand" "") + (match_operand:TI 1 "register_operand" "") + (match_operand:TI 2 "aarch64_reg_or_imm" "") + (match_operand 3 "")] + "" +{ + rtx l0,l1,l2,h0,h1,h2; + + aarch64_add_128bit_scratch_regs (operands[1], operands[2], + &l0, &l1, &l2, &h0, &h1, &h2); + + if (l2 == const0_rtx) + { + l0 = l1; + emit_insn (gen_adddi3_compareC (h0, h1, force_reg (DImode, h2))); + } + else + { + emit_insn (gen_adddi3_compareC (l0, l1, force_reg (DImode, l2))); + emit_insn (gen_adddi3_carryinC (h0, h1, force_reg (DImode, h2))); + } + + emit_move_insn (gen_lowpart (DImode, operands[0]), l0); + emit_move_insn (gen_highpart (DImode, operands[0]), h0); + + aarch64_gen_unlikely_cbranch (NE, CC_Cmode, operands[3]); + DONE; + }) + (define_insn "add3_compare0" [(set (reg:CC_NZ CC_REGNUM) (compare:CC_NZ @@ -1755,7 +1853,7 @@ (define_insn "add3_compareC" [(set (reg:CC_C CC_REGNUM) - (ne:CC_C + (compare:CC_C (plus: (zero_extend: (match_operand:GPI 1 "register_operand" "r")) (zero_extend: (match_operand:GPI 2 "register_operand" "r"))) @@ -1768,10 +1866,70 @@ [(set_attr "type" "alus_sreg")] ) +;; Note that since we're sign-extending, match the immediate in GPI +;; rather than in DWI. Since CONST_INT is modeless, this works fine. +(define_insn "*add3_compareV_cconly_imm" + [(set (reg:CC_V CC_REGNUM) + (compare:CC_V + (plus: + (sign_extend: (match_operand:GPI 0 "register_operand" "r,r")) + (match_operand:GPI 1 "aarch64_plus_immediate" "I,J")) + (sign_extend: (plus:GPI (match_dup 0) (match_dup 1)))))] + "" + "@ + cmn\\t%0, %1 + cmp\\t%0, #%n1" + [(set_attr "type" "alus_imm")] +) + +(define_insn "*add3_compareV_cconly" + [(set (reg:CC_V CC_REGNUM) + (compare:CC_V + (plus: + (sign_extend: (match_operand:GPI 0 "register_operand" "r")) + (sign_extend: (match_operand:GPI 1 "register_operand" "r"))) + (sign_extend: (plus:GPI (match_dup 0) (match_dup 1)))))] + "" + "cmn\\t%0, %1" + [(set_attr "type" "alus_sreg")] +) + +(define_insn "*add3_compareV_imm" + [(set (reg:CC_V CC_REGNUM) + (compare:CC_V + (plus: + (sign_extend: + (match_operand:GPI 1 "register_operand" "r,r")) + (match_operand:GPI 2 "aarch64_plus_immediate" "I,J")) + (sign_extend: + (plus:GPI (match_dup 1) (match_dup 2))))) + (set (match_operand:GPI 0 "register_operand" "=r,r") + (plus:GPI (match_dup 1) (match_dup 2)))] + "" + "@ + adds\\t%0, %1, %2 + subs\\t%0, %1, #%n2" + [(set_attr "type" "alus_imm,alus_imm")] +) + +(define_insn "add3_compareV" + [(set (reg:CC_V CC_REGNUM) + (compare:CC_V + (plus: + (sign_extend: (match_operand:GPI 1 "register_operand" "r")) + (sign_extend: (match_operand:GPI 2 "register_operand" "r"))) + (sign_extend: (plus:GPI (match_dup 1) (match_dup 2))))) + (set (match_operand:GPI 0 "register_operand" "=r") + (plus:GPI (match_dup 1) (match_dup 2)))] + "" + "adds\\t%0, %1, %2" + [(set_attr "type" "alus_sreg")] +) + (define_insn "*adds_shift_imm_" [(set (reg:CC_NZ CC_REGNUM) (compare:CC_NZ - (plus:GPI (ASHIFT:GPI + (plus:GPI (ASHIFT:GPI (match_operand:GPI 1 "register_operand" "r") (match_operand:QI 2 "aarch64_shift_imm_" "n")) (match_operand:GPI 3 "register_operand" "r")) @@ -2138,6 +2296,138 @@ [(set_attr "type" "adc_reg")] ) +(define_expand "add3_carryinC" + [(parallel + [(set (match_dup 3) + (compare:CC_C + (plus: + (plus: + (match_dup 4) + (zero_extend: + (match_operand:GPI 1 "register_operand" ""))) + (zero_extend: + (match_operand:GPI 2 "register_operand" ""))) + (zero_extend: + (plus:GPI + (plus:GPI (match_dup 5) (match_dup 1)) + (match_dup 2))))) + (set (match_operand:GPI 0 "register_operand") + (plus:GPI + (plus:GPI (match_dup 5) (match_dup 1)) + (match_dup 2)))])] + "" +{ + operands[3] = gen_rtx_REG (CC_Cmode, CC_REGNUM); + operands[4] = gen_rtx_NE (mode, operands[3], const0_rtx); + operands[5] = gen_rtx_NE (mode, operands[3], const0_rtx); +}) + +(define_insn "*add3_carryinC_zero" + [(set (reg:CC_C CC_REGNUM) + (compare:CC_C + (plus: + (match_operand: 2 "aarch64_carry_operation" "") + (zero_extend: (match_operand:GPI 1 "register_operand" "r"))) + (zero_extend: + (plus:GPI + (match_operand:GPI 3 "aarch64_carry_operation" "") + (match_dup 1))))) + (set (match_operand:GPI 0 "register_operand") + (plus:GPI (match_dup 3) (match_dup 1)))] + "" + "adcs\\t%0, %1, zr" + [(set_attr "type" "adc_reg")] +) + +(define_insn "*add3_carryinC" + [(set (reg:CC_C CC_REGNUM) + (compare:CC_C + (plus: + (plus: + (match_operand: 3 "aarch64_carry_operation" "") + (zero_extend: (match_operand:GPI 1 "register_operand" "r"))) + (zero_extend: (match_operand:GPI 2 "register_operand" "r"))) + (zero_extend: + (plus:GPI + (plus:GPI + (match_operand:GPI 4 "aarch64_carry_operation" "") + (match_dup 1)) + (match_dup 2))))) + (set (match_operand:GPI 0 "register_operand") + (plus:GPI + (plus:GPI (match_dup 4) (match_dup 1)) + (match_dup 2)))] + "" + "adcs\\t%0, %1, %2" + [(set_attr "type" "adc_reg")] +) + +(define_expand "add3_carryinV" + [(parallel + [(set (reg:CC_V CC_REGNUM) + (compare:CC_V + (plus: + (plus: + (match_dup 3) + (sign_extend: + (match_operand:GPI 1 "register_operand" ""))) + (sign_extend: + (match_operand:GPI 2 "register_operand" ""))) + (sign_extend: + (plus:GPI + (plus:GPI (match_dup 4) (match_dup 1)) + (match_dup 2))))) + (set (match_operand:GPI 0 "register_operand") + (plus:GPI + (plus:GPI (match_dup 4) (match_dup 1)) + (match_dup 2)))])] + "" +{ + rtx cc = gen_rtx_REG (CC_Cmode, CC_REGNUM); + operands[3] = gen_rtx_NE (mode, cc, const0_rtx); + operands[4] = gen_rtx_NE (mode, cc, const0_rtx); +}) + +(define_insn "*add3_carryinV_zero" + [(set (reg:CC_V CC_REGNUM) + (compare:CC_V + (plus: + (match_operand: 2 "aarch64_carry_operation" "") + (sign_extend: (match_operand:GPI 1 "register_operand" "r"))) + (sign_extend: + (plus:GPI + (match_operand:GPI 3 "aarch64_carry_operation" "") + (match_dup 1))))) + (set (match_operand:GPI 0 "register_operand") + (plus:GPI (match_dup 3) (match_dup 1)))] + "" + "adcs\\t%0, %1, zr" + [(set_attr "type" "adc_reg")] +) + +(define_insn "*add3_carryinV" + [(set (reg:CC_V CC_REGNUM) + (compare:CC_V + (plus: + (plus: + (match_operand: 3 "aarch64_carry_operation" "") + (sign_extend: (match_operand:GPI 1 "register_operand" "r"))) + (sign_extend: (match_operand:GPI 2 "register_operand" "r"))) + (sign_extend: + (plus:GPI + (plus:GPI + (match_operand:GPI 4 "aarch64_carry_operation" "") + (match_dup 1)) + (match_dup 2))))) + (set (match_operand:GPI 0 "register_operand") + (plus:GPI + (plus:GPI (match_dup 4) (match_dup 1)) + (match_dup 2)))] + "" + "adcs\\t%0, %1, %2" + [(set_attr "type" "adc_reg")] +) + (define_insn "*add_uxt_shift2" [(set (match_operand:GPI 0 "register_operand" "=rk") (plus:GPI (and:GPI -- 1.9.1