Hello!
New register allocator alternative decorations allows us to not
penalize alternatives *unless* reload is required. The '$' is
described as:
'$'
This constraint is analogous to '!' but it disparages severely the
alternative only if the operand with the '$' needs a reload.
and fits the use case where we want to zero-extend from mem/greg to
XMM register, but not when reload is required. Zero-extension from
general reg -> xmm reg is important after SSE variable shift patterns
were fixed to use DImode value as their count operand.
PR target/80425
* config/i386.i386.md (*zero_extendsidi2): Change (?r,*Yj), (?*Yi,r)
and (*x,m) to ($r,Yj), ($Yi,r) and ($x,m).
(zero-extendsidi peephole2): Remove peephole.
testsuite/ChangeLog:
PR target/80425
* gcc.target/i386/pr80425-3.c: New test.
Patch was bootstrapped and regression tested on x86_64-linux-gnu {,-m32}.
Committed to mainline SVN.
Uros.
Index: config/i386/i386.md
===================================================================
--- config/i386/i386.md (revision 254498)
+++ config/i386/i386.md (working copy)
@@ -3864,10 +3864,10 @@
(define_insn "*zero_extendsidi2"
[(set (match_operand:DI 0 "nonimmediate_operand"
- "=r,?r,?o,r ,o,?*Ym,?!*y,?r ,?*Yi,*x,*x,*v,*r")
+ "=r,?r,?o,r ,o,?*Ym,?!*y,$r,$Yi,$x,*x,*v,*r")
(zero_extend:DI
(match_operand:SI 1 "x86_64_zext_operand"
- "0 ,rm,r ,rmWz,0,r ,m ,*Yj,r ,m ,*x,*v,*k")))]
+ "0 ,rm,r ,rmWz,0,r ,m ,Yj,r ,m ,*x,*v,*k")))]
""
{
switch (get_attr_type (insn))
@@ -3983,15 +3983,6 @@
(set (match_dup 4) (const_int 0))]
"split_double_mode (DImode, &operands[0], 1, &operands[3], &operands[4]);")
-(define_peephole2
- [(set (match_operand:DI 0 "general_reg_operand")
- (zero_extend:DI (match_operand:SI 1 "nonimmediate_gr_operand")))
- (set (match_operand:DI 2 "sse_reg_operand") (match_dup 0))]
- "TARGET_64BIT && TARGET_SSE2 && TARGET_INTER_UNIT_MOVES_TO_VEC
- && peep2_reg_dead_p (2, operands[0])"
- [(set (match_dup 2)
- (zero_extend:DI (match_dup 1)))])
-
(define_mode_attr kmov_isa
[(QI "avx512dq") (HI "avx512f") (SI "avx512bw") (DI "avx512bw")])
Index: testsuite/gcc.target/i386/pr80425-3.c
===================================================================
--- testsuite/gcc.target/i386/pr80425-3.c (nonexistent)
+++ testsuite/gcc.target/i386/pr80425-3.c (working copy)
@@ -0,0 +1,14 @@
+/* { dg-do compile } */
+/* { dg-options "-O2 -mavx512f" } */
+
+#include <x86intrin.h>
+
+extern int a;
+
+__m512i
+f1 (__m512i x)
+{
+ return _mm512_srai_epi32 (x, a);
+}
+
+/* { dg-final { scan-assembler-times "movd\[ \\t\]+\[^\n\]*%xmm" 1 } } */
