On 06/11/17 20:08, Richard Sandiford wrote:
> Some of the shift expanders accepted nonmemory_operands but were only
> able to handle register_operands or CONST_INTs. This is probably
> academic without SVE, since we're not likely to see shifts by other
> types of constant (const_wide_ints, consts, etc). But for SVE,
> it's possible for a vectorised shift induction to have a CONST_POLY_INT
> shift amount.
>
> This patch makes the expanders use aarch64_reg_or_imm instead.
> Tested on aarch64-elf and aarch64-linux-gnu. OK to install?
>
> Richard
>
>
OK.
R.
> 2017-11-06 Richard Sandiford <richard.sandif...@linaro.org>
>
> gcc/
> * config/aarch64/aarch64.md (ashl<mode>3, ashr<mode>3, lshr<mode>3)
> (rotr<mode>3, rotl<mode>3): Use aarch64_reg_or_imm instead of
> nonmmory_operand.
>
> Index: gcc/config/aarch64/aarch64.md
> ===================================================================
> --- gcc/config/aarch64/aarch64.md 2017-11-06 19:39:27.183969328 +0000
> +++ gcc/config/aarch64/aarch64.md 2017-11-06 20:06:43.298665078 +0000
> @@ -3958,7 +3958,7 @@ (define_split
> (define_expand "<optab><mode>3"
> [(set (match_operand:GPI 0 "register_operand")
> (ASHIFT:GPI (match_operand:GPI 1 "register_operand")
> - (match_operand:QI 2 "nonmemory_operand")))]
> + (match_operand:QI 2 "aarch64_reg_or_imm")))]
> ""
> {
> if (CONST_INT_P (operands[2]))
> @@ -3994,7 +3994,7 @@ (define_expand "ashl<mode>3"
> (define_expand "rotr<mode>3"
> [(set (match_operand:GPI 0 "register_operand")
> (rotatert:GPI (match_operand:GPI 1 "register_operand")
> - (match_operand:QI 2 "nonmemory_operand")))]
> + (match_operand:QI 2 "aarch64_reg_or_imm")))]
> ""
> {
> if (CONST_INT_P (operands[2]))
> @@ -4014,7 +4014,7 @@ (define_expand "rotr<mode>3"
> (define_expand "rotl<mode>3"
> [(set (match_operand:GPI 0 "register_operand")
> (rotatert:GPI (match_operand:GPI 1 "register_operand")
> - (match_operand:QI 2 "nonmemory_operand")))]
> + (match_operand:QI 2 "aarch64_reg_or_imm")))]
> ""
> {
> /* (SZ - cnt) % SZ == -cnt % SZ */
>
