From 02000c896ca17ad0cfa301ca993a9ae78defd527 Mon Sep 17 00:00:00 2001 From: julia Date: Fri, 3 Nov 2017 17:50:14 +0300 Subject: [PATCH] fix gfni --- gcc/common/config/i386/i386-common.c | 15 +++++++++------ gcc/config/i386/i386-builtin.def | 16 ++++++++-------- gcc/config/i386/i386-c.c | 4 ++-- gcc/config/i386/i386.c | 20 ++++++++++---------- gcc/config/i386/i386.opt | 4 ++-- 5 files changed, 31 insertions(+), 28 deletions(-) diff --git a/gcc/common/config/i386/i386-common.c b/gcc/common/config/i386/i386-common.c index ada918e..acad248 100644 --- a/gcc/common/config/i386/i386-common.c +++ b/gcc/common/config/i386/i386-common.c @@ -242,8 +242,7 @@ along with GCC; see the file COPYING3. If not see #define OPTION_MASK_ISA_GENERAL_REGS_ONLY_UNSET \ (OPTION_MASK_ISA_MMX_UNSET \ - | OPTION_MASK_ISA_SSE_UNSET \ - | OPTION_MASK_ISA_MPX) + | OPTION_MASK_ISA_SSE_UNSET) /* Implement TARGET_HANDLE_OPTION. */ @@ -265,8 +264,12 @@ ix86_handle_option (struct gcc_options *opts, general registers are allowed. */ opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_GENERAL_REGS_ONLY_UNSET; + opts->x_ix86_isa_flags2 + &= ~OPTION_MASK_ISA_MPX; opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_GENERAL_REGS_ONLY_UNSET; + opts->x_ix86_isa_flags2_explicit + |= OPTION_MASK_ISA_MPX; opts->x_target_flags &= ~MASK_80387; } @@ -493,13 +496,13 @@ ix86_handle_option (struct gcc_options *opts, case OPT_mgfni: if (value) { - opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA_GFNI_SET; - opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA_GFNI_SET; + opts->x_ix86_isa_flags |= OPTION_MASK_ISA_GFNI_SET; + opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_GFNI_SET; } else { - opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA_GFNI_UNSET; - opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA_GFNI_UNSET; + opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_GFNI_UNSET; + opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_GFNI_UNSET; } return true; diff --git a/gcc/config/i386/i386-builtin.def b/gcc/config/i386/i386-builtin.def index 76e5f0f..3cf5eae 100644 --- a/gcc/config/i386/i386-builtin.def +++ b/gcc/config/i386/i386-builtin.def @@ -2394,6 +2394,14 @@ BDESC (OPTION_MASK_ISA_AVX512VBMI | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_ BDESC (OPTION_MASK_ISA_AVX512VBMI | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vpermi2varv32qi3_mask, "__builtin_ia32_vpermi2varqi256_mask", IX86_BUILTIN_VPERMI2VARQI256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI_V32QI_USI) BDESC (OPTION_MASK_ISA_AVX512VBMI | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vpermi2varv16qi3_mask, "__builtin_ia32_vpermi2varqi128_mask", IX86_BUILTIN_VPERMI2VARQI128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI_V16QI_UHI) +/* GFNI */ +BDESC (OPTION_MASK_ISA_GFNI, CODE_FOR_vgf2p8affineinvqb_v64qi, "__builtin_ia32_vgf2p8affineinvqb_v64qi", IX86_BUILTIN_VGF2P8AFFINEINVQB512, UNKNOWN, (int) V64QI_FTYPE_V64QI_V64QI_INT) +BDESC (OPTION_MASK_ISA_GFNI | OPTION_MASK_ISA_AVX512BW, CODE_FOR_vgf2p8affineinvqb_v64qi_mask, "__builtin_ia32_vgf2p8affineinvqb_v64qi_mask", IX86_BUILTIN_VGF2P8AFFINEINVQB512MASK, UNKNOWN, (int) V64QI_FTYPE_V64QI_V64QI_INT_V64QI_UDI) +BDESC (OPTION_MASK_ISA_GFNI | OPTION_MASK_ISA_AVX, CODE_FOR_vgf2p8affineinvqb_v32qi, "__builtin_ia32_vgf2p8affineinvqb_v32qi", IX86_BUILTIN_VGF2P8AFFINEINVQB256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI_INT) +BDESC (OPTION_MASK_ISA_GFNI | OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_vgf2p8affineinvqb_v32qi_mask, "__builtin_ia32_vgf2p8affineinvqb_v32qi_mask", IX86_BUILTIN_VGF2P8AFFINEINVQB256MASK, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI_INT_V32QI_USI) +BDESC (OPTION_MASK_ISA_GFNI | OPTION_MASK_ISA_SSE, CODE_FOR_vgf2p8affineinvqb_v16qi, "__builtin_ia32_vgf2p8affineinvqb_v16qi", IX86_BUILTIN_VGF2P8AFFINEINVQB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI_INT) +BDESC (OPTION_MASK_ISA_GFNI | OPTION_MASK_ISA_SSE, CODE_FOR_vgf2p8affineinvqb_v16qi_mask, "__builtin_ia32_vgf2p8affineinvqb_v16qi_mask", IX86_BUILTIN_VGF2P8AFFINEINVQB128MASK, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI_INT_V16QI_UHI) + /* Builtins with rounding support. */ BDESC_END (ARGS, ROUND_ARGS) @@ -2588,14 +2596,6 @@ BDESC (OPTION_MASK_ISA_AVX512VPOPCNTDQ, CODE_FOR_vpopcountv8di_mask, "__builtin_ /* RDPID */ BDESC (OPTION_MASK_ISA_RDPID, CODE_FOR_rdpid, "__builtin_ia32_rdpid", IX86_BUILTIN_RDPID, UNKNOWN, (int) UNSIGNED_FTYPE_VOID) - -/* GFNI */ -BDESC (OPTION_MASK_ISA_GFNI, CODE_FOR_vgf2p8affineinvqb_v64qi, "__builtin_ia32_vgf2p8affineinvqb_v64qi", IX86_BUILTIN_VGF2P8AFFINEINVQB512, UNKNOWN, (int) V64QI_FTYPE_V64QI_V64QI_INT) -BDESC (OPTION_MASK_ISA_GFNI | OPTION_MASK_ISA_AVX512BW, CODE_FOR_vgf2p8affineinvqb_v64qi_mask, "__builtin_ia32_vgf2p8affineinvqb_v64qi_mask", IX86_BUILTIN_VGF2P8AFFINEINVQB512MASK, UNKNOWN, (int) V64QI_FTYPE_V64QI_V64QI_INT_V64QI_UDI) -BDESC (OPTION_MASK_ISA_GFNI, CODE_FOR_vgf2p8affineinvqb_v32qi, "__builtin_ia32_vgf2p8affineinvqb_v32qi", IX86_BUILTIN_VGF2P8AFFINEINVQB256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI_INT) -BDESC (OPTION_MASK_ISA_GFNI | OPTION_MASK_ISA_AVX512BW, CODE_FOR_vgf2p8affineinvqb_v32qi_mask, "__builtin_ia32_vgf2p8affineinvqb_v32qi_mask", IX86_BUILTIN_VGF2P8AFFINEINVQB256MASK, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI_INT_V32QI_USI) -BDESC (OPTION_MASK_ISA_GFNI, CODE_FOR_vgf2p8affineinvqb_v16qi, "__builtin_ia32_vgf2p8affineinvqb_v16qi", IX86_BUILTIN_VGF2P8AFFINEINVQB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI_INT) -BDESC (OPTION_MASK_ISA_GFNI | OPTION_MASK_ISA_AVX512BW, CODE_FOR_vgf2p8affineinvqb_v16qi_mask, "__builtin_ia32_vgf2p8affineinvqb_v16qi_mask", IX86_BUILTIN_VGF2P8AFFINEINVQB128MASK, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI_INT_V16QI_UHI) BDESC_END (ARGS2, MPX) /* Builtins for MPX. */ diff --git a/gcc/config/i386/i386-c.c b/gcc/config/i386/i386-c.c index 7f88bef..18042cd 100644 --- a/gcc/config/i386/i386-c.c +++ b/gcc/config/i386/i386-c.c @@ -447,7 +447,7 @@ ix86_target_macros_internal (HOST_WIDE_INT isa_flag, def_or_undef (parse_in, "__XSAVEC__"); if (isa_flag & OPTION_MASK_ISA_XSAVES) def_or_undef (parse_in, "__XSAVES__"); - if (isa_flag & OPTION_MASK_ISA_MPX) + if (isa_flag2 & OPTION_MASK_ISA_MPX) def_or_undef (parse_in, "__MPX__"); if (isa_flag & OPTION_MASK_ISA_CLWB) def_or_undef (parse_in, "__CLWB__"); @@ -457,7 +457,7 @@ ix86_target_macros_internal (HOST_WIDE_INT isa_flag, def_or_undef (parse_in, "__PKU__"); if (isa_flag2 & OPTION_MASK_ISA_RDPID) def_or_undef (parse_in, "__RDPID__"); - if (isa_flag2 & OPTION_MASK_ISA_GFNI) + if (isa_flag & OPTION_MASK_ISA_GFNI) def_or_undef (parse_in, "__GFNI__"); if (isa_flag2 & OPTION_MASK_ISA_IBT) { diff --git a/gcc/config/i386/i386.c b/gcc/config/i386/i386.c index 2967872..4b9dc05 100644 --- a/gcc/config/i386/i386.c +++ b/gcc/config/i386/i386.c @@ -2741,7 +2741,7 @@ ix86_target_string (HOST_WIDE_INT isa, HOST_WIDE_INT isa2, ISAs come first. Target string will be displayed in the same order. */ static struct ix86_target_opts isa2_opts[] = { - { "-mgfni", OPTION_MASK_ISA_GFNI }, + { "-mmpx", OPTION_MASK_ISA_MPX }, { "-mrdpid", OPTION_MASK_ISA_RDPID }, { "-msgx", OPTION_MASK_ISA_SGX }, { "-mavx5124vnniw", OPTION_MASK_ISA_AVX5124VNNIW }, @@ -2752,6 +2752,7 @@ ix86_target_string (HOST_WIDE_INT isa, HOST_WIDE_INT isa2, }; static struct ix86_target_opts isa_opts[] = { + { "-mgfni", OPTION_MASK_ISA_GFNI }, { "-mavx512vbmi", OPTION_MASK_ISA_AVX512VBMI }, { "-mavx512ifma", OPTION_MASK_ISA_AVX512IFMA }, { "-mavx512vl", OPTION_MASK_ISA_AVX512VL }, @@ -2809,7 +2810,6 @@ ix86_target_string (HOST_WIDE_INT isa, HOST_WIDE_INT isa2, { "-mlwp", OPTION_MASK_ISA_LWP }, { "-mhle", OPTION_MASK_ISA_HLE }, { "-mfxsr", OPTION_MASK_ISA_FXSR }, - { "-mmpx", OPTION_MASK_ISA_MPX }, { "-mclwb", OPTION_MASK_ISA_CLWB } }; @@ -4077,8 +4077,8 @@ ix86_option_override_internal (bool main_args_p, && !(opts->x_ix86_isa_flags_explicit & OPTION_MASK_ISA_AVX512VL)) opts->x_ix86_isa_flags |= OPTION_MASK_ISA_AVX512VL; if (processor_alias_table[i].flags & PTA_MPX - && !(opts->x_ix86_isa_flags_explicit & OPTION_MASK_ISA_MPX)) - opts->x_ix86_isa_flags |= OPTION_MASK_ISA_MPX; + && !(opts->x_ix86_isa_flags2_explicit & OPTION_MASK_ISA_MPX)) + opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA_MPX; if (processor_alias_table[i].flags & PTA_AVX512VBMI && !(opts->x_ix86_isa_flags_explicit & OPTION_MASK_ISA_AVX512VBMI)) opts->x_ix86_isa_flags |= OPTION_MASK_ISA_AVX512VBMI; @@ -4121,10 +4121,10 @@ ix86_option_override_internal (bool main_args_p, break; } - if (TARGET_X32 && (opts->x_ix86_isa_flags & OPTION_MASK_ISA_MPX)) + if (TARGET_X32 && (opts->x_ix86_isa_flags2 & OPTION_MASK_ISA_MPX)) error ("Intel MPX does not support x32"); - if (TARGET_X32 && (ix86_isa_flags & OPTION_MASK_ISA_MPX)) + if (TARGET_X32 && (ix86_isa_flags2 & OPTION_MASK_ISA_MPX)) error ("Intel MPX does not support x32"); if (i == pta_size) @@ -30734,7 +30734,7 @@ ix86_init_mpx_builtins () continue; ftype = (enum ix86_builtin_func_type) d->flag; - decl = def_builtin (d->mask, d->name, ftype, d->code); + decl = def_builtin2 (d->mask, d->name, ftype, d->code); /* With no leaf and nothrow flags for MPX builtins abnormal edges may follow its call when setjmp @@ -30767,7 +30767,7 @@ ix86_init_mpx_builtins () continue; ftype = (enum ix86_builtin_func_type) d->flag; - decl = def_builtin_const (d->mask, d->name, ftype, d->code); + decl = def_builtin_const2 (d->mask, d->name, ftype, d->code); if (decl) { @@ -35122,10 +35122,10 @@ ix86_expand_builtin (tree exp, rtx target, rtx subtarget, at all, -m64 is a whole TU option. */ if (((ix86_builtins_isa[fcode].isa & ~(OPTION_MASK_ISA_AVX512VL | OPTION_MASK_ISA_MMX - | OPTION_MASK_ISA_64BIT)) + | OPTION_MASK_ISA_64BIT | OPTION_MASK_ISA_GFNI)) && !(ix86_builtins_isa[fcode].isa & ~(OPTION_MASK_ISA_AVX512VL | OPTION_MASK_ISA_MMX - | OPTION_MASK_ISA_64BIT) + | OPTION_MASK_ISA_64BIT | OPTION_MASK_ISA_GFNI) & ix86_isa_flags)) || ((ix86_builtins_isa[fcode].isa & OPTION_MASK_ISA_AVX512VL) && !(ix86_isa_flags & OPTION_MASK_ISA_AVX512VL)) diff --git a/gcc/config/i386/i386.opt b/gcc/config/i386/i386.opt index 7c9dd47..b1bcb39 100644 --- a/gcc/config/i386/i386.opt +++ b/gcc/config/i386/i386.opt @@ -754,7 +754,7 @@ Target Report Mask(ISA_RDPID) Var(ix86_isa_flags2) Save Support RDPID built-in functions and code generation. mgfni -Target Report Mask(ISA_GFNI) Var(ix86_isa_flags2) Save +Target Report Mask(ISA_GFNI) Var(ix86_isa_flags) Save Support GFNI built-in functions and code generation. mbmi @@ -903,7 +903,7 @@ Target Report Mask(ISA_RTM) Var(ix86_isa_flags) Save Support RTM built-in functions and code generation. mmpx -Target Report Mask(ISA_MPX) Var(ix86_isa_flags) Save +Target Report Mask(ISA_MPX) Var(ix86_isa_flags2) Save Support MPX code generation. mmwaitx -- 2.5.5