The SVE port uses the public constraints "Upl" and "Upa" to mean
"low predicate register" and "any predicate register" respectively.
"Upl" was already used as an internal-only constraint by the
addition patterns, so this patch renames it to "Uaa" ("two adds
needed").
2017-10-27 Richard Sandiford <richard.sandif...@linaro.org>
Alan Hayward <alan.hayw...@arm.com>
David Sherwood <david.sherw...@arm.com>
gcc/
* config/aarch64/constraints.md (Upl): Rename to...
(Uaa): ...this.
* config/aarch64/aarch64.md
(*zero_extend<SHORT:mode><GPI:mode>2_aarch64, *addsi3_aarch64_uxtw):
Update accordingly.
Index: gcc/config/aarch64/constraints.md
===================================================================
--- gcc/config/aarch64/constraints.md 2017-10-27 14:06:16.159815485 +0100
+++ gcc/config/aarch64/constraints.md 2017-10-27 14:11:54.071011147 +0100
@@ -35,7 +35,7 @@ (define_constraint "I"
(and (match_code "const_int")
(match_test "aarch64_uimm12_shift (ival)")))
-(define_constraint "Upl"
+(define_constraint "Uaa"
"@internal A constant that matches two uses of add instructions."
(and (match_code "const_int")
(match_test "aarch64_pluslong_strict_immedate (op, VOIDmode)")))
Index: gcc/config/aarch64/aarch64.md
===================================================================
--- gcc/config/aarch64/aarch64.md 2017-10-27 14:07:01.875769946 +0100
+++ gcc/config/aarch64/aarch64.md 2017-10-27 14:11:54.071011147 +0100
@@ -1562,7 +1562,7 @@ (define_insn "*add<mode>3_aarch64"
(match_operand:GPI 0 "register_operand" "=rk,rk,w,rk,r")
(plus:GPI
(match_operand:GPI 1 "register_operand" "%rk,rk,w,rk,rk")
- (match_operand:GPI 2 "aarch64_pluslong_operand" "I,r,w,J,Upl")))]
+ (match_operand:GPI 2 "aarch64_pluslong_operand" "I,r,w,J,Uaa")))]
""
"@
add\\t%<w>0, %<w>1, %2
@@ -1580,7 +1580,7 @@ (define_insn "*addsi3_aarch64_uxtw"
(match_operand:DI 0 "register_operand" "=rk,rk,rk,r")
(zero_extend:DI
(plus:SI (match_operand:SI 1 "register_operand" "%rk,rk,rk,rk")
- (match_operand:SI 2 "aarch64_pluslong_operand" "I,r,J,Upl"))))]
+ (match_operand:SI 2 "aarch64_pluslong_operand" "I,r,J,Uaa"))))]
""
"@
add\\t%w0, %w1, %2
