TARGET_ISEL64 just means TARGET_ISEL && TARGET_POWERPC64. Since
everywhere it is used uses :GPR already, we can just as well use
TARGET_ISEL always.
Tested as usual, committing.
Segher
2017-10-11 Segher Boessenkool <seg...@kernel.crashing.org>
* config/rs6000/rs6000.h (TARGET_ISEL64): Delete.
* config/rs6000/rs6000.md (sel): Delete mode attribute.
(mov<mode>cc, isel_signed_<mode>, isel_unsigned_<mode>,
*isel_reversed_signed_<mode>, *isel_reversed_unsigned_<mode>): Use
TARGET_ISEL instead of TARGET_ISEL<sel>.
---
gcc/config/rs6000/rs6000.h | 2 --
gcc/config/rs6000/rs6000.md | 13 +++++--------
2 files changed, 5 insertions(+), 10 deletions(-)
diff --git a/gcc/config/rs6000/rs6000.h b/gcc/config/rs6000/rs6000.h
index 21e536b..5a5244a 100644
--- a/gcc/config/rs6000/rs6000.h
+++ b/gcc/config/rs6000/rs6000.h
@@ -565,8 +565,6 @@ extern int rs6000_vector_align[];
#define TARGET_ALTIVEC_ABI rs6000_altivec_abi
#define TARGET_LDBRX (TARGET_POPCNTD || rs6000_cpu == PROCESSOR_CELL)
-#define TARGET_ISEL64 (TARGET_ISEL && TARGET_POWERPC64)
-
/* ISA 2.01 allowed FCFID to be done in 32-bit, previously it was 64-bit only.
Enable 32-bit fcfid's on any of the switches for newer ISA machines or
XILINX. */
diff --git a/gcc/config/rs6000/rs6000.md b/gcc/config/rs6000/rs6000.md
index 7e1566a..611aa9d 100644
--- a/gcc/config/rs6000/rs6000.md
+++ b/gcc/config/rs6000/rs6000.md
@@ -578,9 +578,6 @@ (define_mode_attr bits [(QI "8") (HI "16") (SI "32") (DI
"64")])
; DImode bits
(define_mode_attr dbits [(QI "56") (HI "48") (SI "32")])
-;; ISEL/ISEL64 target selection
-(define_mode_attr sel [(SI "") (DI "64")])
-
;; Bitmask for shift instructions
(define_mode_attr hH [(SI "h") (DI "H")])
@@ -4915,7 +4912,7 @@ (define_expand "mov<mode>cc"
(if_then_else:GPR (match_operand 1 "comparison_operator" "")
(match_operand:GPR 2 "gpc_reg_operand" "")
(match_operand:GPR 3 "gpc_reg_operand" "")))]
- "TARGET_ISEL<sel>"
+ "TARGET_ISEL"
"
{
if (rs6000_emit_cmove (operands[0], operands[1], operands[2], operands[3]))
@@ -4940,7 +4937,7 @@ (define_insn "isel_signed_<mode>"
(const_int 0)])
(match_operand:GPR 2 "reg_or_zero_operand" "O,b")
(match_operand:GPR 3 "gpc_reg_operand" "r,r")))]
- "TARGET_ISEL<sel>"
+ "TARGET_ISEL"
"isel %0,%2,%3,%j1"
[(set_attr "type" "isel")])
@@ -4952,7 +4949,7 @@ (define_insn "isel_unsigned_<mode>"
(const_int 0)])
(match_operand:GPR 2 "reg_or_zero_operand" "O,b")
(match_operand:GPR 3 "gpc_reg_operand" "r,r")))]
- "TARGET_ISEL<sel>"
+ "TARGET_ISEL"
"isel %0,%2,%3,%j1"
[(set_attr "type" "isel")])
@@ -4968,7 +4965,7 @@ (define_insn "*isel_reversed_signed_<mode>"
(const_int 0)])
(match_operand:GPR 2 "gpc_reg_operand" "r,r")
(match_operand:GPR 3 "reg_or_zero_operand" "O,b")))]
- "TARGET_ISEL<sel>"
+ "TARGET_ISEL"
{
PUT_CODE (operands[1], reverse_condition (GET_CODE (operands[1])));
return "isel %0,%3,%2,%j1";
@@ -4983,7 +4980,7 @@ (define_insn "*isel_reversed_unsigned_<mode>"
(const_int 0)])
(match_operand:GPR 2 "gpc_reg_operand" "r,r")
(match_operand:GPR 3 "reg_or_zero_operand" "O,b")))]
- "TARGET_ISEL<sel>"
+ "TARGET_ISEL"
{
PUT_CODE (operands[1], reverse_condition (GET_CODE (operands[1])));
return "isel %0,%3,%2,%j1";
--
1.8.3.1
