On Tue, Sep 19, 2017 at 11:17 PM, Uros Bizjak <ubiz...@gmail.com> wrote:
> Hello!
>
> As mentioned in PR 82259. These are similar to existing BT jcc patterns.
>
> 2017-09-19 Uros Bizjak <ubiz...@gmail.com>
>
> * config/i386/i386.md (*scc_bt<mode>): New insn_and_split pattern.
> (*scc_bt<mode>_1): Ditto.
> (*scc_bt<mode>_mask): Ditto.
>
> testsuite/ChangeLog:
>
> 2017-09-19 Uros Bizjak <ubiz...@gmail.com>
>
> * gcc.target/i386/bt-5.c: New test.
> * gcc.target/i386/bt-6.c: Ditto.
> * gcc.target/i386/bt-mask-3.c: Ditto.
> * gcc.target/i386/bt-mask-4.c: Ditto.
>
> Bootstrapped and regression tested on x86_64-linux-gnu {,-m32}.
>
> Committed to mainline SVN.
I have reverted the patch. The combination of shift+and is better than
bt+setcc, since the former avoids partial registers, and allows the
compiler to emit better code when cmove is involved:
sarl %cl, %edi
andl $1, %edi
cmovne %edx, %eax
When patched gcc generates bt insn, following asm is created:
xorl %edx, %edx
btl %esi, %edi
setc %dl
testl %edx, %edx
cmovne %ecx, %eax.
Uros.
