GCC maintianers:
Addressed the comments from Segher about copying operands in
define_expand lxvll and stxvll. Added new temp for the output of the
sldi instructions to give the allocator the freedom to select the
registers. Removed constraints in the expanders. Cleaned up issues
left over from the previous patch version. Removed length attributes
that are now 4 rather then 8.
Tested on
powerpc64le-unknown-linux-gnu (Power 9 LE),
powerpc64le-unknown-linux-gnu (Power 8 LE) and
powerpc64le-unknown-linux-gnu (Power 8 BE) without regressions.
Please let me know if there are any additional issues to address.
----------------------------------------------------------------------------
2017-09-18 Carl Love <c...@us.ibm.com>
* config/rs6000/rs6000-c.c (P9V_BUILTIN_VEC_XL_LEN_R,
P9V_BUILTIN_VEC_XST_LEN_R): Add support for builtins
vector unsigned char vec_xl_len_r (unsigned char *, size_t);
void vec_xst_len_r (vector unsigned char, unsigned char *, size_t);
* config/rs6000/altivec.h (vec_xl_len_r, vec_xst_len_r): Add defines.
* config/rs6000/rs6000-builtin.def (XL_LEN_R, XST_LEN_R): Add
definitions and overloading.
* config/rs6000/rs6000.c (altivec_expand_builtin): Add case
statement for P9V_BUILTIN_XST_LEN_R.
(altivec_init_builtins): Add def_builtin for P9V_BUILTIN_STXVLL.
* config/rs6000/vsx.md (lxvll, stxvll, xl_len_r, xst_len_r): Add
define_expand and define_insn for the instructions and builtins.
* doc/extend.texi: Update the built-in documentation file for the new
built-in functions.
* config/rs6000/altivec.md (altivec_lvsl_reg, altivec_lvsr_reg): Add
define_insn for the instructions
gcc/testsuite/ChangeLog:
2017-09-18 Carl Love <c...@us.ibm.com>
* gcc.target/powerpc/builtins-5-p9-runnable.c: Add new runable test file
for the new built-ins and the existing built-ins.
---
gcc/config/rs6000/altivec.h | 2 +
gcc/config/rs6000/altivec.md | 20 +-
gcc/config/rs6000/rs6000-builtin.def | 4 +
gcc/config/rs6000/rs6000-c.c | 8 +
gcc/config/rs6000/rs6000.c | 11 +-
gcc/config/rs6000/vsx.md | 64 +++++
gcc/doc/extend.texi | 4 +
.../gcc.target/powerpc/builtins-5-p9-runnable.c | 309 +++++++++++++++++++++
8 files changed, 419 insertions(+), 3 deletions(-)
create mode 100644 gcc/testsuite/gcc.target/powerpc/builtins-5-p9-runnable.c
diff --git a/gcc/config/rs6000/altivec.h b/gcc/config/rs6000/altivec.h
index c8e508cf0..94a4db24a 100644
--- a/gcc/config/rs6000/altivec.h
+++ b/gcc/config/rs6000/altivec.h
@@ -467,6 +467,8 @@
#ifdef _ARCH_PPC64
#define vec_xl_len __builtin_vec_lxvl
#define vec_xst_len __builtin_vec_stxvl
+#define vec_xl_len_r __builtin_vec_xl_len_r
+#define vec_xst_len_r __builtin_vec_xst_len_r
#endif
#define vec_cmpnez __builtin_vec_vcmpnez
diff --git a/gcc/config/rs6000/altivec.md b/gcc/config/rs6000/altivec.md
index 0aa1e3016..a01720545 100644
--- a/gcc/config/rs6000/altivec.md
+++ b/gcc/config/rs6000/altivec.md
@@ -2542,6 +2542,15 @@
DONE;
})
+(define_insn "altivec_lvsl_reg"
+ [(set (match_operand:V16QI 0 "altivec_register_operand" "=v")
+ (unspec:V16QI
+ [(match_operand:DI 1 "gpc_reg_operand" "b")]
+ UNSPEC_LVSL_REG))]
+ "TARGET_ALTIVEC"
+ "lvsl %0,0,%1"
+ [(set_attr "type" "vecload")])
+
(define_insn "altivec_lvsl_direct"
[(set (match_operand:V16QI 0 "register_operand" "=v")
(unspec:V16QI [(match_operand:V16QI 1 "memory_operand" "Z")]
@@ -2551,7 +2560,7 @@
[(set_attr "type" "vecload")])
(define_expand "altivec_lvsr"
- [(use (match_operand:V16QI 0 "register_operand" ""))
+ [(use (match_operand:V16QI 0 "altivec_register_operand" ""))
(use (match_operand:V16QI 1 "memory_operand" ""))]
"TARGET_ALTIVEC"
{
@@ -2574,6 +2583,15 @@
DONE;
})
+(define_insn "altivec_lvsr_reg"
+ [(set (match_operand:V16QI 0 "altivec_register_operand" "=v")
+ (unspec:V16QI
+ [(match_operand:DI 1 "gpc_reg_operand" "b")]
+ UNSPEC_LVSR_REG))]
+ "TARGET_ALTIVEC"
+ "lvsr %0,0,%1"
+ [(set_attr "type" "vecload")])
+
(define_insn "altivec_lvsr_direct"
[(set (match_operand:V16QI 0 "register_operand" "=v")
(unspec:V16QI [(match_operand:V16QI 1 "memory_operand" "Z")]
diff --git a/gcc/config/rs6000/rs6000-builtin.def
b/gcc/config/rs6000/rs6000-builtin.def
index 850164a09..8f87ccea4 100644
--- a/gcc/config/rs6000/rs6000-builtin.def
+++ b/gcc/config/rs6000/rs6000-builtin.def
@@ -2125,6 +2125,7 @@ BU_P9V_OVERLOAD_2 (VIESP, "insert_exp_sp")
/* 2 argument vector functions added in ISA 3.0 (power9). */
BU_P9V_64BIT_VSX_2 (LXVL, "lxvl", CONST, lxvl)
+BU_P9V_64BIT_VSX_2 (XL_LEN_R, "xl_len_r", CONST, xl_len_r)
BU_P9V_AV_2 (VEXTUBLX, "vextublx", CONST, vextublx)
BU_P9V_AV_2 (VEXTUBRX, "vextubrx", CONST, vextubrx)
@@ -2141,6 +2142,7 @@ BU_P9V_VSX_3 (VINSERT4B_DI, "vinsert4b_di", CONST,
vinsert4b_di)
/* 3 argument vector functions returning void, treated as SPECIAL,
added in ISA 3.0 (power9). */
BU_P9V_64BIT_AV_X (STXVL, "stxvl", MISC)
+BU_P9V_64BIT_AV_X (XST_LEN_R, "xst_len_r", MISC)
/* 1 argument vector functions added in ISA 3.0 (power9). */
BU_P9V_AV_1 (VCLZLSBB, "vclzlsbb", CONST, vclzlsbb)
@@ -2182,12 +2184,14 @@ BU_P9V_AV_P (VCMPNEZW_P, "vcmpnezw_p", CONST,
vector_nez_v4si_p)
/* ISA 3.0 Vector scalar overloaded 2 argument functions */
BU_P9V_OVERLOAD_2 (LXVL, "lxvl")
+BU_P9V_OVERLOAD_2 (XL_LEN_R, "xl_len_r")
BU_P9V_OVERLOAD_2 (VEXTULX, "vextulx")
BU_P9V_OVERLOAD_2 (VEXTURX, "vexturx")
BU_P9V_OVERLOAD_2 (VEXTRACT4B, "vextract4b")
/* ISA 3.0 Vector scalar overloaded 3 argument functions */
BU_P9V_OVERLOAD_3 (STXVL, "stxvl")
+BU_P9V_OVERLOAD_3 (XST_LEN_R, "xst_len_r")
BU_P9V_OVERLOAD_3 (VINSERT4B, "vinsert4b")
/* Overloaded CMPNE support was implemented prior to Power 9,
diff --git a/gcc/config/rs6000/rs6000-c.c b/gcc/config/rs6000/rs6000-c.c
index b2df850e8..2388260be 100644
--- a/gcc/config/rs6000/rs6000-c.c
+++ b/gcc/config/rs6000/rs6000-c.c
@@ -4789,6 +4789,10 @@ const struct altivec_builtin_types
altivec_overloaded_builtins[] = {
{ P9V_BUILTIN_VEC_VSCEDPUO, P9V_BUILTIN_VSCEDPUO,
RS6000_BTI_INTSI, RS6000_BTI_double, RS6000_BTI_double, 0 },
+ { P9V_BUILTIN_VEC_XL_LEN_R, P9V_BUILTIN_XL_LEN_R,
+ RS6000_BTI_unsigned_V16QI, ~RS6000_BTI_UINTQI,
+ RS6000_BTI_unsigned_long_long, 0 },
+
{ P9V_BUILTIN_VEC_LXVL, P9V_BUILTIN_LXVL,
RS6000_BTI_V16QI, ~RS6000_BTI_INTQI,
RS6000_BTI_unsigned_long_long, 0 },
@@ -4833,6 +4837,10 @@ const struct altivec_builtin_types
altivec_overloaded_builtins[] = {
/* At an appropriate future time, add support for the
RS6000_BTI_Float16 (exact name to be determined) type here. */
+ { P9V_BUILTIN_VEC_XST_LEN_R, P9V_BUILTIN_XST_LEN_R,
+ RS6000_BTI_void, RS6000_BTI_unsigned_V16QI,
+ ~RS6000_BTI_UINTQI, RS6000_BTI_unsigned_long_long},
+
{ P9V_BUILTIN_VEC_STXVL, P9V_BUILTIN_STXVL,
RS6000_BTI_void, RS6000_BTI_V16QI, ~RS6000_BTI_INTQI,
RS6000_BTI_unsigned_long_long },
diff --git a/gcc/config/rs6000/rs6000.c b/gcc/config/rs6000/rs6000.c
index ecdf776b9..10919edc7 100644
--- a/gcc/config/rs6000/rs6000.c
+++ b/gcc/config/rs6000/rs6000.c
@@ -15546,6 +15546,9 @@ altivec_expand_builtin (tree exp, rtx target, bool
*expandedp)
case P9V_BUILTIN_STXVL:
return altivec_expand_stxvl_builtin (CODE_FOR_stxvl, exp);
+ case P9V_BUILTIN_XST_LEN_R:
+ return altivec_expand_stxvl_builtin (CODE_FOR_xst_len_r, exp);
+
case VSX_BUILTIN_STXVD2X_V1TI:
return altivec_expand_stv_builtin (CODE_FOR_vsx_store_v1ti, exp);
case VSX_BUILTIN_STXVD2X_V2DF:
@@ -17488,8 +17491,12 @@ altivec_init_builtins (void)
def_builtin ("__builtin_vec_stvrxl", void_ftype_v16qi_long_pvoid,
ALTIVEC_BUILTIN_VEC_STVRXL);
if (TARGET_P9_VECTOR)
- def_builtin ("__builtin_altivec_stxvl", void_ftype_v16qi_pvoid_long,
- P9V_BUILTIN_STXVL);
+ {
+ def_builtin ("__builtin_altivec_stxvl", void_ftype_v16qi_pvoid_long,
+ P9V_BUILTIN_STXVL);
+ def_builtin ("__builtin_xst_len_r", void_ftype_v16qi_pvoid_long,
+ P9V_BUILTIN_XST_LEN_R);
+ }
/* Add the DST variants. */
d = bdesc_dst;
diff --git a/gcc/config/rs6000/vsx.md b/gcc/config/rs6000/vsx.md
index 9b24c7b72..c5e56e96e 100644
--- a/gcc/config/rs6000/vsx.md
+++ b/gcc/config/rs6000/vsx.md
@@ -382,8 +382,16 @@
UNSPEC_VSX_VTSTDC
UNSPEC_VSX_VEC_INIT
UNSPEC_VSX_VSIGNED2
+
UNSPEC_LXVL
+ UNSPEC_LXVLL
+ UNSPEC_LVSL_REG
+ UNSPEC_LVSR_REG
UNSPEC_STXVL
+ UNSPEC_STXVLL
+ UNSPEC_XL_LEN_R
+ UNSPEC_XST_LEN_R
+
UNSPEC_VCLZLSBB
UNSPEC_VCTZLSBB
UNSPEC_VEXTUBLX
@@ -4352,6 +4360,43 @@
[(set_attr "length" "8")
(set_attr "type" "vecload")])
+(define_insn "lxvll"
+ [(set (match_operand:V16QI 0 "vsx_register_operand" "=wa")
+ (unspec:V16QI [(match_operand:DI 1 "gpc_reg_operand" "b")
+ (match_operand:DI 2 "register_operand" "r")]
+ UNSPEC_LXVLL))]
+ "TARGET_P9_VECTOR"
+ "lxvll %x0,%1,%2"
+ [(set_attr "type" "vecload")])
+
+;; Expand for builtin xl_len_r
+(define_expand "xl_len_r"
+ [(match_operand:V16QI 0 "vsx_register_operand" "=wa")
+ (match_operand:DI 1 "register_operand" "b")
+ (match_operand:DI 2 "register_operand" "r")]
+ ""
+{
+ rtx shift_mask = gen_reg_rtx (V16QImode);
+ rtx rtx_vtmp = gen_reg_rtx (V16QImode);
+ rtx tmp = gen_reg_rtx (DImode);
+
+ emit_insn (gen_altivec_lvsl_reg (shift_mask, operands[2]));
+ emit_insn (gen_ashldi3 (tmp, operands[2], GEN_INT (56)));
+ emit_insn (gen_lxvll (rtx_vtmp, operands[1], tmp));
+ emit_insn (gen_altivec_vperm_v8hiv16qi (operands[0], rtx_vtmp, rtx_vtmp,
+ shift_mask));
+ DONE;
+})
+
+(define_insn "stxvll"
+ [(set (mem:V16QI (match_operand:DI 1 "gpc_reg_operand" "b"))
+ (unspec:V16QI [(match_operand:V16QI 0 "vsx_register_operand" "wa")
+ (match_operand:DI 2 "register_operand" "r")]
+ UNSPEC_STXVLL))]
+ "TARGET_P9_VECTOR"
+ "stxvll %x0,%1,%2"
+ [(set_attr "type" "vecstore")])
+
;; Store VSX Vector with Length
(define_expand "stxvl"
[(set (match_dup 3)
@@ -4377,6 +4422,25 @@
[(set_attr "length" "8")
(set_attr "type" "vecstore")])
+;; Expand for builtin xst_len_r
+(define_expand "xst_len_r"
+ [(match_operand:V16QI 0 "vsx_register_operand" "=wa")
+ (match_operand:DI 1 "register_operand" "b")
+ (match_operand:DI 2 "register_operand" "r")]
+ "UNSPEC_XST_LEN_R"
+{
+ rtx shift_mask = gen_reg_rtx (V16QImode);
+ rtx rtx_vtmp = gen_reg_rtx (V16QImode);
+ rtx tmp = gen_reg_rtx (DImode);
+
+ emit_insn (gen_altivec_lvsr_reg (shift_mask, operands[2]));
+ emit_insn (gen_altivec_vperm_v8hiv16qi (rtx_vtmp, operands[0], operands[0],
+ shift_mask));
+ emit_insn (gen_ashldi3 (tmp, operands[2], GEN_INT (56)));
+ emit_insn (gen_stxvll (rtx_vtmp, operands[1], tmp));
+ DONE;
+})
+
;; Vector Compare Not Equal Byte
(define_insn "vcmpneb"
[(set (match_operand:V16QI 0 "altivec_register_operand" "=v")
diff --git a/gcc/doc/extend.texi b/gcc/doc/extend.texi
index 649be015d..37fd769df 100644
--- a/gcc/doc/extend.texi
+++ b/gcc/doc/extend.texi
@@ -15631,6 +15631,8 @@ vector unsigned short vec_xl_len (unsigned short *addr,
size_t len);
vector double vec_xl_len (double *addr, size_t len);
vector float vec_xl_len (float *addr, size_t len);
+vector unsigned char vec_xl_len_r (unsigned char *addr, size_t len);
+
void vec_xst_len (vector signed char data, signed char *addr, size_t len);
void vec_xst_len (vector unsigned char data, unsigned char *addr, size_t len);
void vec_xst_len (vector signed int data, signed int *addr, size_t len);
@@ -15644,6 +15646,8 @@ void vec_xst_len (vector signed __int128 data, signed
__int128 *addr, size_t len
void vec_xst_len (vector double data, double *addr, size_t len);
void vec_xst_len (vector float data, float *addr, size_t len);
+void vec_xst_len_r (vector unsigned char data, unsigned char *addr, size_t
len);
+
signed char vec_xlx (unsigned int index, vector signed char data);
unsigned char vec_xlx (unsigned int index, vector unsigned char data);
signed short vec_xlx (unsigned int index, vector signed short data);
diff --git a/gcc/testsuite/gcc.target/powerpc/builtins-5-p9-runnable.c
b/gcc/testsuite/gcc.target/powerpc/builtins-5-p9-runnable.c
new file mode 100644
index 000000000..ad3947196
--- /dev/null
+++ b/gcc/testsuite/gcc.target/powerpc/builtins-5-p9-runnable.c
@@ -0,0 +1,309 @@
+/* { dg-do run { target { powerpc*-*-* && p9vector_hw } } } */
+/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } {
"-mcpu=power9" } } */
+/* { dg-options "-mcpu=power9 -O2" } */
+
+#include <stdint.h>
+#include <stdio.h>
+#include <inttypes.h>
+#include <altivec.h> // vector
+
+#define TRUE 1
+#define FALSE 0
+
+#ifdef DEBUG
+#include <stdio.h>
+#endif
+
+void abort (void);
+
+int result_wrong(vector unsigned char vec_expected,
+ vector unsigned char vec_actual)
+{
+ int i;
+
+ for (i=0; i<16; i++)
+ if (vec_expected[i] != vec_actual[i])
+ return TRUE;
+
+ return FALSE;
+}
+
+int main() {
+ int i, j;
+ size_t size;
+ unsigned char data_uc[100];
+ vector unsigned char store_data_uc;
+ unsigned char *address;
+ vector unsigned char *datap;
+
+ vector unsigned char vec_uc_expected1, vec_uc_expected2,
+ vec_uc_result1, vec_uc_result2;
+ vector int data_int;
+
+ for (i=0; i<100; i++)
+ data_uc[i] = i+1;
+
+
+ /* VEC_XL_LEN */
+
+ size = 8;
+ vec_uc_result1 = vec_xl_len (data_uc, size);
+
+ vec_uc_expected1 = (vector unsigned char){ 1, 2, 3, 4, 5, 6, 7, 8,
+ 0, 0, 0, 0, 0, 0, 0, 0};
+
+ if (result_wrong (vec_uc_expected1, vec_uc_result1))
+ {
+#ifdef DEBUG
+ printf("Error: result does not match expected result\n");
+ printf("vec_xl_len (%d): vec_uc_expected1[0] to vec_uc_expected1[15]\n",
+ size);
+
+ for (i=0; i<16; i++)
+ printf(" %d,",vec_uc_expected1[i]);
+
+ printf("\nvec_xl_len (%d): vec_uc_result1[0] to vec_uc_result1[15]\n",
+ size);
+
+ for (i=0; i<16; i++)
+ printf(" %d,", vec_uc_result1[i]);
+
+ printf("\n\n");
+#else
+ abort();
+#endif
+ }
+
+
+ /* VEC_XL_LEN_R */
+ size = 8;
+ vec_uc_result2 = vec_xl_len_r(data_uc, size);
+
+ vec_uc_expected2 = (vector unsigned char){8, 7, 6, 5, 4, 3, 2, 1,
+ 0, 0, 0, 0, 0, 0, 0, 0,};
+
+ if (result_wrong (vec_uc_expected2, vec_uc_result2))
+ {
+#ifdef DEBUG
+ printf("Error: result does not match expected result\n");
+ printf("vec_xl_len_r(%d): vec_uc_expected2[0] to
vec_uc_expected2[15]\n",
+ size);
+
+ for (i=0; i<16; i++)
+ printf(" %d,", vec_uc_expected2[i]);
+
+ printf("\nvec_xl_len_r(%d): vec_uc_result2[0] to vec_uc_result2[15]\n",
+ size);
+
+ for (i=0; i<16; i++)
+ printf(" %d,", vec_uc_result2[i]);
+
+ printf("\n\n");
+#else
+ abort();
+#endif
+ }
+
+
+ size = 4;
+ vec_uc_result2 = vec_xl_len_r(data_uc, size);
+
+ vec_uc_expected2 = (vector unsigned char){ 4, 3, 2, 1, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0 };
+
+ if (result_wrong (vec_uc_expected2, vec_uc_result2))
+ {
+#ifdef DEBUG
+ printf("Error: result does not match expected result\n");
+ printf("vec_xl_len_r(%d): vec_uc_expected2[0] to
vec_uc_expected2[15]\n",
+ size);
+
+ for (i=0; i<16; i++)
+ printf(" %d,", vec_uc_expected2[i]);
+
+ printf("\nvec_xl_len_r(%d): vec_uc_result2[0] to vec_uc_result2[15]\n",
+ size);
+
+ for (i=0; i<16; i++)
+ printf(" %d,", vec_uc_result2[i]);
+
+ printf("\n\n");
+#else
+ abort();
+#endif
+ }
+
+ size = 2;
+ vec_uc_result2 = vec_xl_len_r(data_uc, size);
+
+ vec_uc_expected2 = (vector unsigned char){ 2, 1, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0 };
+
+ if (result_wrong (vec_uc_expected2, vec_uc_result2))
+ {
+#ifdef DEBUG
+ printf("Error: result does not match expected result\n");
+ printf("vec_xl_len_r(%d): vec_uc_expected2[0] to
vec_uc_expected2[15]\n",
+ size);
+ for (i=0; i<16; i++)
+ printf(" %d,", vec_uc_expected2[i]);
+
+ printf("\nvec_xl_len_r(%d) vec_uc_result2[0] to vec_uc_result2[15]\n",
+ size);
+
+ for (i=0; i<16; i++)
+ printf(" %d,", vec_uc_result2[i]);
+
+ printf("\n\n");
+#else
+ abort();
+#endif
+ }
+
+
+ /* VEC_XST_LEN */
+ vec_uc_expected2 = (vector unsigned char){ 1, 2, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0 };
+ store_data_uc = (vector unsigned char){ 1, 2, 3, 4, 5, 6, 7, 8,
+ 9, 10, 11, 12, 13, 14, 15, 16 };
+ size = 2;
+
+ for (i=0; i<16; i++)
+ vec_uc_result2[i] = 0;
+
+ address = &vec_uc_result2[0];
+ vec_xst_len (store_data_uc, address, size);
+
+ if (result_wrong (vec_uc_expected2, vec_uc_result2))
+ {
+#ifdef DEBUG
+ printf("Error: result does not match expected result\n");
+ printf("vec_xst_len (%d) vec_uc_result2[0] to vec_uc_result2[15]\n",
+ size);
+
+ for (i=0; i<16; i++)
+ printf(" %d,", vec_uc_expected2[i]);
+
+ printf("\nvec_xst_len (%d) store_data_uc[0] to store_data_uc[15]\n",
+ size);
+
+ for (i=0; i<16; i++)
+ printf(" %d,", vec_uc_result2[i]);
+
+ printf("\n\n");
+#else
+ abort();
+#endif
+ }
+
+ vec_uc_expected2 = (vector unsigned char){ 1, 2, 3, 4, 5, 6, 7, 8,
+ 9, 10, 11, 12, 13, 14, 0, 0 };
+ store_data_uc = (vector unsigned char){ 1, 2, 3, 4, 5, 6, 7, 8,
+ 9, 10, 11, 12, 13, 14, 15, 16 };
+ size = 14;
+
+ for (i=0; i<16; i++)
+ vec_uc_result2[i] = 0;
+
+ address = &vec_uc_result2[0];
+
+ vec_xst_len (store_data_uc, address, size);
+
+ if (result_wrong (vec_uc_expected2, vec_uc_result2))
+ {
+#ifdef DEBUG
+ printf("Error: result does not match expected result\n");
+ printf("vec_xst_len (%d) vec_uc_result2[0] to vec_uc_result2[15]\n",
+ size);
+
+ for (i=0; i<16; i++)
+ printf(" %d,", vec_uc_expected2[i]);
+
+ printf("\nvec_xst_len (%d) store_data_uc[0] to store_data_uc[15]\n",
+ size);
+
+ for (i=0; i<16; i++)
+ printf(" %d,", vec_uc_result2[i]);
+
+ printf("\n\n");
+#else
+ abort();
+#endif
+ }
+
+ /* VEC_XST_LEN_R */
+ vec_uc_expected1 = (vector unsigned char){ 2, 1, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0 };
+ store_data_uc = (vector unsigned char){ 1, 2, 3, 4, 5, 6, 7, 8,
+ 9, 10, 11, 12, 13, 14, 15, 16 };
+ vec_uc_result1 = (vector unsigned char){ 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0 };
+
+ size = 2;
+
+ for (i=0; i<16; i++)
+ vec_uc_result1[i] = 0;
+
+ address = &vec_uc_result1[0];
+
+ vec_xst_len_r(store_data_uc, address, size);
+
+ if (result_wrong (vec_uc_expected1, vec_uc_result1))
+ {
+#ifdef DEBUG
+ printf("Error: result does not match expected result\n");
+ printf("vec_xst_len_r(%d) vec_uc_expected1[0] to
vec_uc_expected1[15]\n",
+ size);
+
+ for (i=0; i<16; i++)
+ printf(" %d,", vec_uc_expected1[i]);
+
+ printf("\nvec_xst_len_r(%d) result[0] to result[15]\n", size);
+
+ for (i=0; i<16; i++)
+ printf(" %d,", vec_uc_result1[i]);
+
+ printf("\n\n");
+#else
+ abort();
+#endif
+ }
+
+
+ vec_uc_expected1 = (vector unsigned char){ 14, 13, 12, 11, 10, 9, 8, 7,
+ 6, 5, 4, 3, 2, 1, 0, 0 };
+ store_data_uc = (vector unsigned char){ 1, 2, 3, 4, 5, 6, 7, 8,
+ 9, 10, 11, 12, 13, 14, 15, 16 };
+ vec_uc_result1 = (vector unsigned char){ 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0 };
+
+ size = 14;
+
+ for (i=0; i<16; i++)
+ vec_uc_result1[i] = 0;
+
+ address = &vec_uc_result1[0];
+
+ vec_xst_len_r(store_data_uc, address, size);
+
+ if (result_wrong (vec_uc_expected1, vec_uc_result1))
+ {
+#ifdef DEBUG
+ printf("Error: result does not match expected result\n");
+ printf("vec_xst_len_r(%d) vec_uc_expected2[0] to
vec_uc_expected2[15]\n",
+ size);
+
+ for (i=0; i<16; i++)
+ printf(" %d,", vec_uc_expected2[i]);
+
+ printf("\nvec_xst_len_r(%d) result[0] to result[15]\n", size);
+
+ for (i=0; i<16; i++)
+ printf(" %d,", vec_uc_result1[i]);
+
+ printf("\n\n");
+#else
+ abort();
+#endif
+ }
+}
--
2.11.0
