This patch eliminates the undocumented debugging options -mpower9-dform,
-mpower9-dform-scalar, and -mpower9-dform-vector. These switches were added
when I added the support for the ISA 3.0 (power9) d-form (register+offset)
vector addressing.
I have built and bootstrapped compilers on a little endian power8 system and
there were no regressions in the tests. Can I check it into the trunk?
[gcc]
2017-08-23 Michael Meissner <meiss...@linux.vnet.ibm.com>
* config/rs6000/rs6000.opt (-mpower9-dform-scalar): Delete
undocumented switches.
(-mpower9-dform-vector): Likewise.
(-mpower9-dform): Likewise.
* config/rs6000/rs6000-c.c (rs6000_target_modify_macros): Update
comments to delete references to -mpower9-dform* switches.
* config/rs6000/predicates.md (vsx_quad_dform_memory_operand):
Delete reference to -mpower9-dform* switches, test for
-mpower9-vector instead.
* config/rs6000/rs6000-cpus.def (ISA_3_0_MASKS_SERVER): Likewise.
(OTHER_P9_VECTOR_MASKS): Likewise.
(POWERPC_MASKS): Likewise.
* config/rs6000/rs6000.c (rs6000_setup_reg_addr_masks): Change
tests against -mpowwer9-dform* to -mpower9-vector. Delete code
that checked for -mpower9-dform* consistancy with other options.
(rs6000_init_hard_regno_mode_ok): Likewise.
(rs6000_option_override_internal): Likewise.
(rs6000_emit_prologue): Likewise.
(rs6000_emit_epilogue): Likewise.
(rs6000_opt_masks): Delete -mpower9-dform-{scalar,vector}.
(rs6000_disable_incompatiable_switches): Delete -mpower9-dform.
(emit_fusion_p9_load): Change tests for -mpower9-dform-scalar
-mpower9-vector.
(emit_fusion_p9_store): Likewise.
* config/rs6000/rs6000.h (TARGET_P9_DFORM_SCALAR): Delete
resetting these macros if the assembler does not support ISA 3.0
instructions.
(TARGET_P9_DFORM_VECTOR): Likewise.
* config/rs6000/rs6000.md (peepholes to optimize altivec memory):
Change to use -mpower9-vector instead of -mpower9-dform-scalar.
[gcc/testsuite]
2017-08-23 Michael Meissner <meiss...@linux.vnet.ibm.com>
* gcc.target/powerpc/dform-1.c: Delete -mpower9-dform*
options.
* gcc.target/powerpc/dform-2.c: Likewise.
* gcc.target/powerpc/dform-3.c: Likewise.
* gcc.target/powerpc/pr71656-1.c: Likewise.
* gcc.target/powerpc/pr71656-2.c: Likewise.
* gcc.target/powerpc/pr80103-1.c: Likewise.
* gcc.target/powerpc/pr80098-1.c: Likewise.
--
Michael Meissner, IBM
IBM, M/S 2506R, 550 King Street, Littleton, MA 01460-6245, USA
email: meiss...@linux.vnet.ibm.com, phone: +1 (978) 899-4797
Index: gcc/config/rs6000/rs6000.opt
===================================================================
--- gcc/config/rs6000/rs6000.opt
(.../svn+ssh://meiss...@gcc.gnu.org/svn/gcc/trunk/gcc/config/rs6000)
(revision 251248)
+++ gcc/config/rs6000/rs6000.opt (.../gcc/config/rs6000) (working copy)
@@ -550,18 +550,6 @@ mpower9-vector
Target Undocumented Report Mask(P9_VECTOR) Var(rs6000_isa_flags)
Use vector instructions added in ISA 3.0.
-mpower9-dform-scalar
-Target Undocumented Mask(P9_DFORM_SCALAR) Var(rs6000_isa_flags)
-Use scalar register+offset memory instructions added in ISA 3.0.
-
-mpower9-dform-vector
-Target Undocumented Mask(P9_DFORM_VECTOR) Var(rs6000_isa_flags)
-Use vector register+offset memory instructions added in ISA 3.0.
-
-mpower9-dform
-Target Undocumented Report Var(TARGET_P9_DFORM_BOTH) Init(-1) Save
-Use register+offset memory instructions added in ISA 3.0.
-
mpower9-minmax
Target Undocumented Mask(P9_MINMAX) Var(rs6000_isa_flags)
Use the new min/max instructions defined in ISA 3.0.
Index: gcc/config/rs6000/rs6000-c.c
===================================================================
--- gcc/config/rs6000/rs6000-c.c
(.../svn+ssh://meiss...@gcc.gnu.org/svn/gcc/trunk/gcc/config/rs6000)
(revision 251248)
+++ gcc/config/rs6000/rs6000-c.c (.../gcc/config/rs6000) (working copy)
@@ -430,8 +430,8 @@ rs6000_target_modify_macros (bool define
rs6000_define_or_undefine_macro (define_p, "_ARCH_PWR7");
/* Note that the OPTION_MASK_DIRECT_MOVE flag is automatically
turned on in the following condition:
- 1. TARGET_P9_DFORM_SCALAR or TARGET_P9_DFORM_VECTOR are enabled
- and OPTION_MASK_DIRECT_MOVE is not explicitly disabled.
+ 1. TARGET_P8_VECTOR is enabled and OPTION_MASK_DIRECT_MOVE is not
+ explicitly disabled.
Hereafter, the OPTION_MASK_DIRECT_MOVE flag is considered to
have been turned on explicitly.
Note that the OPTION_MASK_DIRECT_MOVE flag is automatically
@@ -545,8 +545,7 @@ rs6000_target_modify_macros (bool define
also considered to have been turned off explicitly.
Note that the OPTION_MASK_P9_VECTOR is automatically turned on
in the following conditions:
- 1. If TARGET_P9_DFORM_SCALAR or TARGET_P9_DFORM_VECTOR and
- OPTION_MASK_P9_VECTOR was not turned off explicitly.
+ 1. If TARGET_P9_MINMAX was turned on explicitly.
Hereafter, THE OPTION_MASK_P9_VECTOR flag is considered to
have been turned on explicitly. */
if ((flags & OPTION_MASK_P9_VECTOR) != 0)
Index: gcc/config/rs6000/predicates.md
===================================================================
--- gcc/config/rs6000/predicates.md
(.../svn+ssh://meiss...@gcc.gnu.org/svn/gcc/trunk/gcc/config/rs6000)
(revision 251248)
+++ gcc/config/rs6000/predicates.md (.../gcc/config/rs6000) (working copy)
@@ -827,7 +827,7 @@ (define_predicate "quad_memory_operand"
(define_predicate "vsx_quad_dform_memory_operand"
(match_code "mem")
{
- if (!TARGET_P9_DFORM_VECTOR || !MEM_P (op) || GET_MODE_SIZE (mode) != 16)
+ if (!TARGET_P9_VECTOR || !MEM_P (op) || GET_MODE_SIZE (mode) != 16)
return false;
return quad_address_p (XEXP (op, 0), mode, false);
Index: gcc/config/rs6000/rs6000-cpus.def
===================================================================
--- gcc/config/rs6000/rs6000-cpus.def
(.../svn+ssh://meiss...@gcc.gnu.org/svn/gcc/trunk/gcc/config/rs6000)
(revision 251248)
+++ gcc/config/rs6000/rs6000-cpus.def (.../gcc/config/rs6000) (working copy)
@@ -61,8 +61,6 @@
| OPTION_MASK_ISEL \
| OPTION_MASK_MODULO \
| OPTION_MASK_P9_FUSION \
- | OPTION_MASK_P9_DFORM_SCALAR \
- | OPTION_MASK_P9_DFORM_VECTOR \
| OPTION_MASK_P9_MINMAX \
| OPTION_MASK_P9_MISC \
| OPTION_MASK_P9_VECTOR)
@@ -76,8 +74,6 @@
/* Flags that need to be turned off if -mno-power9-vector. */
#define OTHER_P9_VECTOR_MASKS (OPTION_MASK_FLOAT128_HW \
- | OPTION_MASK_P9_DFORM_SCALAR \
- | OPTION_MASK_P9_DFORM_VECTOR \
| OPTION_MASK_P9_MINMAX)
/* Flags that need to be turned off if -mno-power8-vector. */
@@ -127,8 +123,6 @@
| OPTION_MASK_NO_UPDATE \
| OPTION_MASK_P8_FUSION \
| OPTION_MASK_P8_VECTOR \
- | OPTION_MASK_P9_DFORM_SCALAR \
- | OPTION_MASK_P9_DFORM_VECTOR \
| OPTION_MASK_P9_FUSION \
| OPTION_MASK_P9_MINMAX \
| OPTION_MASK_P9_MISC \
Index: gcc/config/rs6000/rs6000.c
===================================================================
--- gcc/config/rs6000/rs6000.c
(.../svn+ssh://meiss...@gcc.gnu.org/svn/gcc/trunk/gcc/config/rs6000)
(revision 251248)
+++ gcc/config/rs6000/rs6000.c (.../gcc/config/rs6000) (working copy)
@@ -2926,8 +2926,7 @@ rs6000_setup_reg_addr_masks (void)
&& (rc == RELOAD_REG_GPR
|| ((msize == 8 || m2 == SFmode)
&& (rc == RELOAD_REG_FPR
- || (rc == RELOAD_REG_VMX
- && TARGET_P9_DFORM_SCALAR)))))
+ || (rc == RELOAD_REG_VMX && TARGET_P9_VECTOR)))))
addr_mask |= RELOAD_REG_OFFSET;
/* VSX registers can do REG+OFFSET addresssing if ISA 3.0
@@ -2935,7 +2934,7 @@ rs6000_setup_reg_addr_masks (void)
only 12-bits. While GPRs can handle the full offset range, VSX
registers can only handle the restricted range. */
else if ((addr_mask != 0) && !indexed_only_p
- && msize == 16 && TARGET_P9_DFORM_VECTOR
+ && msize == 16 && TARGET_P9_VECTOR
&& (ALTIVEC_OR_VSX_VECTOR_MODE (m2)
|| (m2 == TImode && TARGET_VSX)))
{
@@ -3255,13 +3254,14 @@ rs6000_init_hard_regno_mode_ok (bool glo
rs6000_constraints[RS6000_CONSTRAINT_wp] = VSX_REGS; /* TFmode */
}
- /* Support for new D-form instructions. */
- if (TARGET_P9_DFORM_SCALAR)
- rs6000_constraints[RS6000_CONSTRAINT_wb] = ALTIVEC_REGS;
-
- /* Support for ISA 3.0 (power9) vectors. */
if (TARGET_P9_VECTOR)
- rs6000_constraints[RS6000_CONSTRAINT_wo] = VSX_REGS;
+ {
+ /* Support for new D-form instructions. */
+ rs6000_constraints[RS6000_CONSTRAINT_wb] = ALTIVEC_REGS;
+
+ /* Support for ISA 3.0 (power9) vectors. */
+ rs6000_constraints[RS6000_CONSTRAINT_wo] = VSX_REGS;
+ }
/* Support for new direct moves (ISA 3.0 + 64bit). */
if (TARGET_DIRECT_MOVE_128)
@@ -3542,7 +3542,7 @@ rs6000_init_hard_regno_mode_ok (bool glo
reg_addr[xmode].fusion_addis_ld[rtype] = addis_insns[i].load;
reg_addr[xmode].fusion_addis_st[rtype] = addis_insns[i].store;
- if (rtype == RELOAD_REG_FPR && TARGET_P9_DFORM_SCALAR)
+ if (rtype == RELOAD_REG_FPR && TARGET_P9_VECTOR)
{
reg_addr[xmode].fusion_addis_ld[RELOAD_REG_VMX]
= addis_insns[i].load;
@@ -4239,8 +4239,7 @@ rs6000_option_override_internal (bool gl
/* For the newer switches (vsx, dfp, etc.) set some of the older options,
unless the user explicitly used the -mno-<option> to disable the code. */
- if (TARGET_P9_VECTOR || TARGET_MODULO || TARGET_P9_DFORM_SCALAR
- || TARGET_P9_DFORM_VECTOR || TARGET_P9_DFORM_BOTH > 0)
+ if (TARGET_P9_VECTOR || TARGET_MODULO || TARGET_P9_MISC)
rs6000_isa_flags |= (ISA_3_0_MASKS_SERVER & ~ignore_masks);
else if (TARGET_P9_MINMAX)
{
@@ -4467,81 +4466,6 @@ rs6000_option_override_internal (bool gl
}
}
- /* -mpower9-dform turns on both -mpower9-dform-scalar and
- -mpower9-dform-vector. */
- if (TARGET_P9_DFORM_BOTH > 0)
- {
- if (!(rs6000_isa_flags_explicit & OPTION_MASK_P9_DFORM_VECTOR))
- rs6000_isa_flags |= OPTION_MASK_P9_DFORM_VECTOR;
-
- if (!(rs6000_isa_flags_explicit & OPTION_MASK_P9_DFORM_SCALAR))
- rs6000_isa_flags |= OPTION_MASK_P9_DFORM_SCALAR;
- }
- else if (TARGET_P9_DFORM_BOTH == 0)
- {
- if (!(rs6000_isa_flags_explicit & OPTION_MASK_P9_DFORM_VECTOR))
- rs6000_isa_flags &= ~OPTION_MASK_P9_DFORM_VECTOR;
-
- if (!(rs6000_isa_flags_explicit & OPTION_MASK_P9_DFORM_SCALAR))
- rs6000_isa_flags &= ~OPTION_MASK_P9_DFORM_SCALAR;
- }
-
- /* ISA 3.0 D-form instructions require p9-vector and upper-regs. */
- if ((TARGET_P9_DFORM_SCALAR || TARGET_P9_DFORM_VECTOR) && !TARGET_P9_VECTOR)
- {
- /* We prefer to not mention undocumented options in
- error messages. However, if users have managed to select
- power9-dform without selecting power9-vector, they
- already know about undocumented flags. */
- if ((rs6000_isa_flags_explicit & OPTION_MASK_P9_VECTOR)
- && (rs6000_isa_flags_explicit & (OPTION_MASK_P9_DFORM_SCALAR
- | OPTION_MASK_P9_DFORM_VECTOR)))
- error ("%qs requires %qs", "-mpower9-dform", "-mpower9-vector");
- else if (rs6000_isa_flags_explicit & OPTION_MASK_P9_VECTOR)
- {
- rs6000_isa_flags &=
- ~(OPTION_MASK_P9_DFORM_SCALAR | OPTION_MASK_P9_DFORM_VECTOR);
- rs6000_isa_flags_explicit |=
- (OPTION_MASK_P9_DFORM_SCALAR | OPTION_MASK_P9_DFORM_VECTOR);
- }
- else
- {
- /* We know that OPTION_MASK_P9_VECTOR is not explicit and
- OPTION_MASK_P9_DFORM_SCALAR or OPTION_MASK_P9_DORM_VECTOR
- may be explicit. */
- rs6000_isa_flags |= OPTION_MASK_P9_VECTOR;
- rs6000_isa_flags_explicit |= OPTION_MASK_P9_VECTOR;
- }
- }
-
- if ((TARGET_P9_DFORM_SCALAR || TARGET_P9_DFORM_VECTOR)
- && !TARGET_DIRECT_MOVE)
- {
- /* We prefer to not mention undocumented options in
- error messages. However, if users have managed to select
- power9-dform without selecting direct-move, they
- already know about undocumented flags. */
- if ((rs6000_isa_flags_explicit & OPTION_MASK_DIRECT_MOVE)
- && ((rs6000_isa_flags_explicit & OPTION_MASK_P9_DFORM_VECTOR) ||
- (rs6000_isa_flags_explicit & OPTION_MASK_P9_DFORM_SCALAR) ||
- (TARGET_P9_DFORM_BOTH == 1)))
- error ("%qs, %qs, %qs require %qs", "-mpower9-dform",
- "-mpower9-dform-vector", "-mpower9-dform-scalar",
- "-mdirect-move");
- else if ((rs6000_isa_flags_explicit & OPTION_MASK_DIRECT_MOVE) == 0)
- {
- rs6000_isa_flags |= OPTION_MASK_DIRECT_MOVE;
- rs6000_isa_flags_explicit |= OPTION_MASK_DIRECT_MOVE;
- }
- else
- {
- rs6000_isa_flags &=
- ~(OPTION_MASK_P9_DFORM_SCALAR | OPTION_MASK_P9_DFORM_VECTOR);
- rs6000_isa_flags_explicit |=
- (OPTION_MASK_P9_DFORM_SCALAR | OPTION_MASK_P9_DFORM_VECTOR);
- }
- }
-
/* Set -mallow-movmisalign to explicitly on if we have full ISA 2.07
support. If we only have ISA 2.06 support, and the user did not specify
the switch, leave it set to -1 so the movmisalign patterns are enabled,
@@ -27386,7 +27310,7 @@ rs6000_emit_prologue (void)
savereg = gen_rtx_REG (V4SImode, i);
- if (TARGET_P9_DFORM_VECTOR && quad_address_offset_p (offset))
+ if (TARGET_P9_VECTOR && quad_address_offset_p (offset))
{
mem = gen_frame_mem (V4SImode,
gen_rtx_PLUS (Pmode, frame_reg_rtx,
@@ -28077,7 +28001,7 @@ rs6000_emit_epilogue (int sibcall)
= (info->altivec_save_offset + frame_off
+ 16 * (i - info->first_altivec_reg_save));
- if (TARGET_P9_DFORM_VECTOR && quad_address_offset_p (offset))
+ if (TARGET_P9_VECTOR && quad_address_offset_p (offset))
{
mem = gen_frame_mem (V4SImode,
gen_rtx_PLUS (Pmode, frame_reg_rtx,
@@ -28293,7 +28217,7 @@ rs6000_emit_epilogue (int sibcall)
= (info->altivec_save_offset + frame_off
+ 16 * (i - info->first_altivec_reg_save));
- if (TARGET_P9_DFORM_VECTOR && quad_address_offset_p (offset))
+ if (TARGET_P9_VECTOR && quad_address_offset_p (offset))
{
mem = gen_frame_mem (V4SImode,
gen_rtx_PLUS (Pmode, frame_reg_rtx,
@@ -36155,8 +36079,6 @@ static struct rs6000_opt_mask const rs60
{ "power8-fusion", OPTION_MASK_P8_FUSION, false, true },
{ "power8-fusion-sign", OPTION_MASK_P8_FUSION_SIGN, false, true },
{ "power8-vector", OPTION_MASK_P8_VECTOR, false, true },
- { "power9-dform-scalar", OPTION_MASK_P9_DFORM_SCALAR, false, true },
- { "power9-dform-vector", OPTION_MASK_P9_DFORM_VECTOR, false, true },
{ "power9-fusion", OPTION_MASK_P9_FUSION, false, true },
{ "power9-minmax", OPTION_MASK_P9_MINMAX, false, true },
{ "power9-misc", OPTION_MASK_P9_MISC, false, true },
@@ -36944,14 +36866,6 @@ rs6000_disable_incompatible_switches (vo
}
}
- if (!TARGET_P9_VECTOR
- && (rs6000_isa_flags_explicit & OPTION_MASK_P9_VECTOR) != 0
- && TARGET_P9_DFORM_BOTH > 0)
- {
- error ("%qs turns off %qs", "-mno-power9-vector", "-mpower9-dform");
- TARGET_P9_DFORM_BOTH = 0;
- }
-
return ignore_masks;
}
@@ -38691,7 +38605,7 @@ emit_fusion_p9_load (rtx reg, rtx mem, r
else
gcc_unreachable ();
}
- else if (ALTIVEC_REGNO_P (r) && TARGET_P9_DFORM_SCALAR)
+ else if (ALTIVEC_REGNO_P (r) && TARGET_P9_VECTOR)
{
if (mode == SFmode)
load_string = "lxssp";
@@ -38778,7 +38692,7 @@ emit_fusion_p9_store (rtx mem, rtx reg,
else
gcc_unreachable ();
}
- else if (ALTIVEC_REGNO_P (r) && TARGET_P9_DFORM_SCALAR)
+ else if (ALTIVEC_REGNO_P (r) && TARGET_P9_VECTOR)
{
if (mode == SFmode)
store_string = "stxssp";
Index: gcc/config/rs6000/rs6000.h
===================================================================
--- gcc/config/rs6000/rs6000.h
(.../svn+ssh://meiss...@gcc.gnu.org/svn/gcc/trunk/gcc/config/rs6000)
(revision 251248)
+++ gcc/config/rs6000/rs6000.h (.../gcc/config/rs6000) (working copy)
@@ -312,15 +312,11 @@ extern const char *host_detect_local_cpu
#undef TARGET_MODULO
#undef TARGET_P9_VECTOR
#undef TARGET_P9_MINMAX
-#undef TARGET_P9_DFORM_SCALAR
-#undef TARGET_P9_DFORM_VECTOR
#undef TARGET_P9_MISC
#define TARGET_FLOAT128_HW 0
#define TARGET_MODULO 0
#define TARGET_P9_VECTOR 0
#define TARGET_P9_MINMAX 0
-#define TARGET_P9_DFORM_SCALAR 0
-#define TARGET_P9_DFORM_VECTOR 0
#define TARGET_P9_MISC 0
#endif
Index: gcc/config/rs6000/rs6000.md
===================================================================
--- gcc/config/rs6000/rs6000.md
(.../svn+ssh://meiss...@gcc.gnu.org/svn/gcc/trunk/gcc/config/rs6000)
(revision 251248)
+++ gcc/config/rs6000/rs6000.md (.../gcc/config/rs6000) (working copy)
@@ -13965,7 +13965,7 @@ (define_peephole2
(match_operand:ALTIVEC_DFORM 2 "simple_offsettable_mem_operand"))
(set (match_operand:ALTIVEC_DFORM 3 "altivec_register_operand")
(match_dup 1))]
- "TARGET_VSX && !TARGET_P9_DFORM_SCALAR && peep2_reg_dead_p (2, operands[1])"
+ "TARGET_VSX && !TARGET_P9_VECTOR && peep2_reg_dead_p (2, operands[1])"
[(set (match_dup 0)
(match_dup 4))
(set (match_dup 3)
@@ -14001,7 +14001,7 @@ (define_peephole2
(match_operand:ALTIVEC_DFORM 2 "altivec_register_operand"))
(set (match_operand:ALTIVEC_DFORM 3 "simple_offsettable_mem_operand")
(match_dup 1))]
- "TARGET_VSX && !TARGET_P9_DFORM_SCALAR && peep2_reg_dead_p (2, operands[1])"
+ "TARGET_VSX && !TARGET_P9_VECTOR && peep2_reg_dead_p (2, operands[1])"
[(set (match_dup 0)
(match_dup 4))
(set (match_dup 5)
Index: gcc/testsuite/gcc.target/powerpc/dform-1.c
===================================================================
--- gcc/testsuite/gcc.target/powerpc/dform-1.c
(.../svn+ssh://meiss...@gcc.gnu.org/svn/gcc/trunk/gcc/testsuite/gcc.target/powerpc)
(revision 251248)
+++ gcc/testsuite/gcc.target/powerpc/dform-1.c
(.../gcc/testsuite/gcc.target/powerpc) (working copy)
@@ -1,7 +1,6 @@
/* { dg-do compile { target { powerpc*-*-* && lp64 } } } */
/* { dg-require-effective-target powerpc_p9vector_ok } */
-/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } {
"-mcpu=power9" } } */
-/* { dg-options "-mcpu=power9 -mpower9-dform -O2" } */
+/* { dg-options "-mpower9-vector -O2" } */
#ifndef TYPE
#define TYPE double
Index: gcc/testsuite/gcc.target/powerpc/dform-2.c
===================================================================
--- gcc/testsuite/gcc.target/powerpc/dform-2.c
(.../svn+ssh://meiss...@gcc.gnu.org/svn/gcc/trunk/gcc/testsuite/gcc.target/powerpc)
(revision 251248)
+++ gcc/testsuite/gcc.target/powerpc/dform-2.c
(.../gcc/testsuite/gcc.target/powerpc) (working copy)
@@ -1,7 +1,6 @@
/* { dg-do compile { target { powerpc*-*-* && lp64 } } } */
/* { dg-require-effective-target powerpc_p9vector_ok } */
-/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } {
"-mcpu=power9" } } */
-/* { dg-options "-mcpu=power9 -mpower9-dform -O2" } */
+/* { dg-options "-mpower9-vector -O2" } */
#ifndef TYPE
#define TYPE float
Index: gcc/testsuite/gcc.target/powerpc/pr71656-1.c
===================================================================
--- gcc/testsuite/gcc.target/powerpc/pr71656-1.c
(.../svn+ssh://meiss...@gcc.gnu.org/svn/gcc/trunk/gcc/testsuite/gcc.target/powerpc)
(revision 251248)
+++ gcc/testsuite/gcc.target/powerpc/pr71656-1.c
(.../gcc/testsuite/gcc.target/powerpc) (working copy)
@@ -1,8 +1,7 @@
/* Test for reload ICE arising from POWER9 Vector Dform code generation. */
/* { dg-do compile } */
/* { dg-require-effective-target powerpc_p9vector_ok } */
-/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } {
"-mcpu=power9" } } */
-/* { dg-options "-O1 -mcpu=power9 -mpower9-dform-vector" } */
+/* { dg-options "-O1 -mpower9-vector" } */
typedef __attribute__((altivec(vector__))) int type_t;
type_t
Index: gcc/testsuite/gcc.target/powerpc/dform-3.c
===================================================================
--- gcc/testsuite/gcc.target/powerpc/dform-3.c
(.../svn+ssh://meiss...@gcc.gnu.org/svn/gcc/trunk/gcc/testsuite/gcc.target/powerpc)
(revision 251248)
+++ gcc/testsuite/gcc.target/powerpc/dform-3.c
(.../gcc/testsuite/gcc.target/powerpc) (working copy)
@@ -1,7 +1,7 @@
/* { dg-do compile { target { powerpc*-*-* && lp64 } } } */
/* { dg-require-effective-target powerpc_p9vector_ok } */
/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } {
"-mcpu=power9" } } */
-/* { dg-options "-mcpu=power9 -mpower9-dform -O2" } */
+/* { dg-options "-mcpu=power9 -O2" } */
#ifndef TYPE
#define TYPE vector double
Index: gcc/testsuite/gcc.target/powerpc/pr71656-2.c
===================================================================
--- gcc/testsuite/gcc.target/powerpc/pr71656-2.c
(.../svn+ssh://meiss...@gcc.gnu.org/svn/gcc/trunk/gcc/testsuite/gcc.target/powerpc)
(revision 251248)
+++ gcc/testsuite/gcc.target/powerpc/pr71656-2.c
(.../gcc/testsuite/gcc.target/powerpc) (working copy)
@@ -1,8 +1,7 @@
/* Test for reload ICE arising from POWER9 Vector Dform code generation. */
/* { dg-do compile } */
/* { dg-require-effective-target powerpc_p9vector_ok } */
-/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } {
"-mcpu=power9" } } */
-/* { dg-options "-O3 -mcpu=power9 -mpower9-dform-vector -funroll-loops
-fno-aggressive-loop-optimizations" } */
+/* { dg-options "-O3 -mpower9-vector -funroll-loops
-fno-aggressive-loop-optimizations" } */
typedef double vec[3];
struct vec_t
Index: gcc/testsuite/gcc.target/powerpc/pr80103-1.c
===================================================================
--- gcc/testsuite/gcc.target/powerpc/pr80103-1.c
(.../svn+ssh://meiss...@gcc.gnu.org/svn/gcc/trunk/gcc/testsuite/gcc.target/powerpc)
(revision 251248)
+++ gcc/testsuite/gcc.target/powerpc/pr80103-1.c
(.../gcc/testsuite/gcc.target/powerpc) (working copy)
@@ -1,13 +1,12 @@
/* { dg-do compile { target { powerpc*-*-* } } } */
/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } {
"-mcpu=power9" } } */
/* { dg-require-effective-target powerpc_p9vector_ok } */
-/* { dg-options "-mpower9-dform-vector -mno-direct-move" } */
+/* { dg-options "-mpower9-minmax -mno-direct-move" } */
/* { dg-excess-errors "expect error due to conflicting target options" } */
/* Since the error message is not associated with a particular line
number, we cannot use the dg-error directive and cannot specify a
regexp to describe the expected error message. The expected error
- message is: "-mpower9-dform, -mpower9-dform-vector,
- -mpower9-dform-scalar require -mdirect-move" */
+ message is: "-mpower9-minmax requires -mdirect-move" */
int a;
void b (__attribute__ ((__vector_size__ (16))) char c)
Index: gcc/testsuite/gcc.target/powerpc/pr80098-1.c
===================================================================
--- gcc/testsuite/gcc.target/powerpc/pr80098-1.c
(.../svn+ssh://meiss...@gcc.gnu.org/svn/gcc/trunk/gcc/testsuite/gcc.target/powerpc)
(revision 251248)
+++ gcc/testsuite/gcc.target/powerpc/pr80098-1.c
(.../gcc/testsuite/gcc.target/powerpc) (working copy)
@@ -1,9 +1,8 @@
/* { dg-do compile { target { powerpc64*-*-* } } } */
/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } {
"-mcpu=power9" } } */
/* { dg-require-effective-target powerpc_p9vector_ok } */
-/* { dg-options "-mcpu=power9 -mno-power9-vector -mpower9-minmax
-mpower9-dform" } */
+/* { dg-options "-mcpu=power9 -mno-power9-vector -mpower9-minmax" } */
int i;
/* { dg-error "'-mno-power9-vector' turns off '-mpower9-minmax'" "PR80098" {
target *-*-* } 0 } */
-/* { dg-error "'-mno-power9-vector' turns off '-mpower9-dform'" "PR80098" {
target *-*-* } 0 } */
