On Mon, Jun 12, 2017 at 01:01:36PM -0700, Carl E. Love wrote:
> * config/rs6000/rs6000-c.c: Add definitions for the vec_float,
> vec_float2, vec_floato, vec_floate built-ins.
> * config/rs6000/vsx.md: Add RTL code for instructions vsx_xvcvsxws
> vsx_xvcvuxwsp, float2, floato and floate.
> * config/rs6000/rs6000-builtin.def: Add definitions for vsx_xvcvsxwsp,
> vsx_xvcvuxwsp, float2, floato and floate.
> * config/altivec.md: Add version of p8_vmrgew that takes V4SF args and
> returns V4SF.
> * config/rs6000/altivec.h: Add builtin defines for vec_float,
> vec_float2, vec_floate and vec_floato.
* config/rs6000/some.thing (name1, name2, name3): ...
(for all of the above).
> Signed-off-by: Carl Love <ca...@us.ibm.com>
No sign-offs for GCC :-)
> + /* The destination of the vmrgew instruction layout is:
> + rtx_tmp2[0] rtx_tmp3[0] rtx_tmp2[1] rtx_tmp3[0].
> + Setup rtx_tmp0 and rtx_tmp1 to ensure the order of the elements after
> the
> + vmrgew instruction will be correct. */
> + if (VECTOR_ELT_ORDER_BIG)
> + {
> + emit_insn (gen_vsx_xxpermdi_v2di_be (rtx_tmp0, src1, src2,
> GEN_INT(0)));
> + emit_insn (gen_vsx_xxpermdi_v2di_be (rtx_tmp1, src1, src2,
> GEN_INT(3)));
There should be a space after GEN_INT. Only when *defining* a function-like
macro there is no space (because there cannot be, in that case).
> --- a/gcc/config/rs6000/vsx.md
> +++ b/gcc/config/rs6000/vsx.md
> @@ -310,6 +310,9 @@
> ;; Iterator for the 2 short vector types to do a splat from an integer
> (define_mode_iterator VSX_SPLAT_I [V16QI V8HI])
>
> +;; Mode attribute for vector floate and floato conversions
> +(define_mode_attr VFC_inst [(V2DI "sxd") (V2DF "dp")])
Is there any reason to not make this similar to VS_sxwsp?
> +(define_insn "vsx_xvcvsxwsp"
> + [(set (match_operand:V4SF 0 "vsx_register_operand" "=wa")
> + (unspec:V4SF[(match_operand:V4SI 1 "vsx_register_operand" "wa")]
> + UNSPEC_VSX_CVSXWSP))]
There should be a space before [.
> +;; Generate float2
> +;; convert two long long signed ints to float
> +(define_expand "float2_v2di"
> + [(use (match_operand:V4SF 0 "register_operand" "=wa"))
> + (use (match_operand:V2DI 1 "register_operand" "wa"))
> + (use (match_operand:V2DI 2 "register_operand" "wa"))]
> + "TARGET_VSX"
You still use TARGET_VSX here, but VECTOR_UNIT_VSX_P (V4SFmode) in the
define_insns this define_expand expands to.
> + if (VECTOR_ELT_ORDER_BIG)
> + {
> + emit_insn (gen_vsx_xvcvuxdsp (operands[0], operands[1]));
> + }
Don't make a block for single insns.
Segher
