Bernd Schmidt <ber...@codesourcery.com> writes: > On 09/14/11 11:03, Richard Sandiford wrote: >> ...I didn't see from an admittedly quick read of the patch how you >> handle memory disambiguation between iterations. If a loop includes: >> >> lb $3,($4) >> sb $5,1($4) >> >> then the two instructions can be reordered by normal ebb scheduling, >> but the inter-iteration conflict is important for modulo scheduling. > > There's nothing special to handle, I think. sched-deps should see that > the ld in iteration 1 is DEP_ANTI against the sb in iteration 0 > (assuming there's also an increment).
For the record, I don't agree that we should rely on register dependencies to handle memory dependencies. It's possible for MEMs in different iterations to alias without there being a register dependence between them. It might not happen often in modulo-schedulable loops, but it is possible... I realise the patch has been approved though. Like I say, it's just for the record. Richard
