On Mon, May 22, 2017 at 02:32:44PM -0400, Michael Meissner wrote: > The register allocator did not use the load with splat instruction (LXVDSX) > because all of the loads were register+offset. For the scalar values that it > could load into the FPR registers, it used the normal register+offset load > (d-form). For the other scalar values that would wind up in the traditional > Altivec registers, the register allocator decided to load up the value into a > GPR register and do a direct move.
> The patch splits the splat into a register splat and a memory splat. This > forces the register allocator to convert the load to the indexed form which > the > LXVDSX instruction uses. > Can I apply this patch to the trunk, and later apply it to the GCC 7 and 6 > branches? Please add a comment near the new instruction patterns saying why reg and mem are separate. Okay for trunk and backports with that. Thanks! Segher > [gcc] > 2017-05-22 Michael Meissner <meiss...@linux.vnet.ibm.com> > > PR target/80718 > * config/rs6000/vsx.md (vsx_splat_<mode>, VSX_D iterator): Split > V2DF/V2DI splat into two separate patterns, one that handles > registers, and the other that only handles memory. Drop support > for splatting from a GPR on ISA 2.07 and then splitting the > splat into direct move and splat. > (vsx_splat_<mode>_reg): Likewise. > (vsx_splat_<mode>_mem): Likewise. > > [gcc/testsuite] > 2017-05-22 Michael Meissner <meiss...@linux.vnet.ibm.com> > > PR target/80718 > * gcc.target/powerpc/pr80718.c: New test.
