On 05/05/2017 01:23 AM, Richard Sandiford wrote:
If we decide to allocate a call-clobbered register R to a value that is live across a call, LRA will create a new spill register TMPR, insert:TMPR <- R before the call and R <- TMPR after it. But if we then failed to allocate a register to TMPR, we would always spill it to the stack, even if R was known to be equivalent to a constant or to some existing memory location. And on AArch64, we'd always fail to allocate such a register for 128-bit Advanced SIMD modes, since no registers of those modes are call-preserved. This patch avoids the problem by copying the equivalence information from the original pseudo to the spill register. It means that the code for the testcase is as good with -O2 as it is with -O, whereas previously the -O code was better. Tested on aarch64-linux-gnu and x86_64-linux-gnu. OK to install? Thanks, Richard [Based on commit branches/ARM/sve-branch@247248] 2017-05-05 Richard Sandiford <richard.sandif...@linaro.org> gcc/ * lra-constraints.c (lra_copy_reg_equiv): New function. (split_reg): Use it to copy equivalence information from the original register to the spill register. gcc/testsuite/ * gcc.target/aarch64/spill_1.c: New test.
OK. jeff
