Hello!
Attached patch makes TARGET_INTER_UNIT_CONVERSIONS setting more
robust, by taking the same approach as handling of
TARGET_INTER_UNIT_{TO,FROM}_VEC.
The patch also removes now obsolete test that checked
TARGET_INTER_UNIT_CONVERSIONS with tune_for_speed attribute, which is
not case anymore.
2017-04-20 Uros Bizjak <ubiz...@gmail.com>
PR target/78090
* config/i386/constraints.md (Yc): New register constraint.
* config/i386/i386.md (*float<SWI48:mode><MODEF:mode>2_mixed):
Use Yc constraint for alternative 2 of operand 0. Remove
preferred_for_speed attribute.
testsuite/ChangeLog:
2017-04-20 Uros Bizjak <ubiz...@gmail.com>
PR target/78090
* gcc.target/i386/conversion-2.c: Remove obsolete test.
Patch was bootstrapped and regression tested on x86_64-linux-gnu {,-m32}.
Committed to mainline SVN.
Uros.
Index: config/i386/constraints.md
===================================================================
--- config/i386/constraints.md (revision 247026)
+++ config/i386/constraints.md (working copy)
@@ -99,6 +99,7 @@
;; We use the Y prefix to denote any number of conditional register sets:
;; z First SSE register.
+;; c SSE inter-unit conversions enabled
;; i SSE2 inter-unit moves to SSE register enabled
;; j SSE2 inter-unit moves from SSE register enabled
;; m MMX inter-unit moves to MMX register enabled
@@ -117,6 +118,10 @@
(define_register_constraint "Yz" "TARGET_SSE ? SSE_FIRST_REG : NO_REGS"
"First SSE register (@code{%xmm0}).")
+(define_register_constraint "Yc"
+ "TARGET_SSE && TARGET_INTER_UNIT_CONVERSIONS ? ALL_SSE_REGS : NO_REGS"
+ "@internal Any SSE register, when SSE and inter-unit conversions are
enabled.")
+
(define_register_constraint "Yi"
"TARGET_SSE2 && TARGET_INTER_UNIT_MOVES_TO_VEC ? ALL_SSE_REGS : NO_REGS"
"@internal Any SSE register, when SSE2 and inter-unit moves to vector
registers are enabled.")
Index: config/i386/i386.md
===================================================================
--- config/i386/i386.md (revision 247026)
+++ config/i386/i386.md (working copy)
@@ -5207,7 +5207,7 @@
})
(define_insn "*float<SWI48:mode><MODEF:mode>2_mixed"
- [(set (match_operand:MODEF 0 "register_operand" "=f,v,v")
+ [(set (match_operand:MODEF 0 "register_operand" "=f,Yc,v")
(float:MODEF
(match_operand:SWI48 1 "nonimmediate_operand" "m,r,m")))]
"SSE_FLOAT_MODE_P (<MODEF:MODE>mode) && TARGET_SSE_MATH"
@@ -5236,10 +5236,6 @@
&& X87_ENABLE_FLOAT (<MODEF:MODE>mode,
<SWI48:MODE>mode)")
]
- (symbol_ref "true")))
- (set (attr "preferred_for_speed")
- (cond [(eq_attr "alternative" "1")
- (symbol_ref "TARGET_INTER_UNIT_CONVERSIONS")]
(symbol_ref "true")))])
(define_insn "*float<SWI48x:mode><MODEF:mode>2_i387"
Index: testsuite/gcc.target/i386/conversion-2.c
===================================================================
--- testsuite/gcc.target/i386/conversion-2.c (revision 247026)
+++ testsuite/gcc.target/i386/conversion-2.c (nonexistent)
@@ -1,36 +0,0 @@
-/* { dg-do compile } */
-/* { dg-options "-O2 -fno-toplevel-reorder -mtune=bdver2" } */
-/* { dg-additional-options "-mregparm=1 -msse -mfpmath=sse" { target ia32 } }
*/
-
-void __attribute__ ((hot))
-f1 (int x)
-{
- register float f asm ("%xmm0") = x;
- asm volatile ("" :: "x" (f));
-}
-
-void __attribute__ ((cold))
-f2 (int x)
-{
- register float f asm ("%xmm1") = x;
- asm volatile ("" :: "x" (f));
-}
-
-void __attribute__ ((hot))
-f3 (int x)
-{
- register float f asm ("%xmm2") = x;
- asm volatile ("" :: "x" (f));
-}
-
-void __attribute__ ((cold))
-f4 (int x)
-{
- register float f asm ("%xmm3") = x;
- asm volatile ("" :: "x" (f));
-}
-
-/* { dg-final { scan-assembler "sp\\\), %xmm0" } } */
-/* { dg-final { scan-assembler "(ax|di), %xmm1" } } */
-/* { dg-final { scan-assembler "sp\\\), %xmm2" } } */
-/* { dg-final { scan-assembler "(ax|di), %xmm3" } } */
