On Nov 13 2016, Eric Botcazou <ebotca...@adacore.com> wrote: > Index: config/aarch64/aarch64.c > =================================================================== > --- config/aarch64/aarch64.c (revision 242334) > +++ config/aarch64/aarch64.c (working copy) > @@ -14502,6 +14502,10 @@ aarch64_optab_supported_p (int op, machi > #undef TARGET_OMIT_STRUCT_RETURN_REG > #define TARGET_OMIT_STRUCT_RETURN_REG true > > +/* The architecture reserves bits 0 and 1 so use bit 2 for descriptors. */ > +#undef TARGET_CUSTOM_FUNCTION_DESCRIPTORS > +#define TARGET_CUSTOM_FUNCTION_DESCRIPTORS 4
In which way are the bits reserved? This does not work for ILP32, because the descriptor address starts off at address 4 modulo 8, and adding 4 clears the bit. Andreas. -- Andreas Schwab, SUSE Labs, sch...@suse.de GPG Key fingerprint = 0196 BAD8 1CE9 1970 F4BE 1748 E4D4 88E3 0EEA B9D7 "And now for something completely different."
