GCC maintainers:
The following patch fixes an issue with the entries in the table of
built-in functions. All of the entries for a given built-in, must occur
in the table as a single block of entries. Otherwise the code that
searches the table for a given built-in definition will stop looking
once it reaches the end of the initial block of definitions for that
built-in function and subsequent definitions for that built-in will
never be checked. This issue currently occurs with the
ALTIVEC_BUILTIN_VEC_PACKS and P8V_BUILTIN_VEC_VGBBD built-ins. The
patch simply moves the existing entries so the definition for a given
built-in are all together in the same block of entries.
Note this issue also exists with the GCC-5 and GCC-6 branches.
The patch has been tested on powerpc64le-unknown-linux-gnu (Power 8 LE)
with no regressions.
Is the patch OK for trunk?
Assuming this patch is OK, would it be acceptable to post a back port of
the patch for GCC 5 and GCC 6 branches after the patch is in mainline as
long as no issues are seen with this version in the mainline code base?
Carl Love
----------------------------------------------------
gcc/ChangeLog:
2017-01-23 Carl Love <c...@us.ibm.com>
* config/rs6000/rs6000-c (altivec_overloaded_builtins): Fix order
of entries for ALTIVEC_BUILTIN_VEC_PACKS and P8V_BUILTIN_VEC_VGBBD.
---
gcc/config/rs6000/rs6000-c.c | 17 ++++++++---------
1 file changed, 8 insertions(+), 9 deletions(-)
diff --git a/gcc/config/rs6000/rs6000-c.c b/gcc/config/rs6000/rs6000-c.c
index 8b87a0a..92e9849 100644
--- a/gcc/config/rs6000/rs6000-c.c
+++ b/gcc/config/rs6000/rs6000-c.c
@@ -2154,14 +2154,14 @@ const struct altivec_builtin_types
altivec_overloaded_builtins[] = {
RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V4SI,
RS6000_BTI_unsigned_V4SI, 0 },
{ ALTIVEC_BUILTIN_VEC_PACKS, ALTIVEC_BUILTIN_VPKSWSS,
RS6000_BTI_V8HI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 },
- { ALTIVEC_BUILTIN_VEC_VPKSWSS, ALTIVEC_BUILTIN_VPKSWSS,
- RS6000_BTI_V8HI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 },
- { ALTIVEC_BUILTIN_VEC_VPKUWUS, ALTIVEC_BUILTIN_VPKUWUS,
- RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V4SI,
RS6000_BTI_unsigned_V4SI, 0 },
{ ALTIVEC_BUILTIN_VEC_PACKS, P8V_BUILTIN_VPKUDUS,
RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V2DI,
RS6000_BTI_unsigned_V2DI, 0 },
{ ALTIVEC_BUILTIN_VEC_PACKS, P8V_BUILTIN_VPKSDSS,
RS6000_BTI_V4SI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0 },
+ { ALTIVEC_BUILTIN_VEC_VPKSWSS, ALTIVEC_BUILTIN_VPKSWSS,
+ RS6000_BTI_V8HI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 },
+ { ALTIVEC_BUILTIN_VEC_VPKUWUS, ALTIVEC_BUILTIN_VPKUWUS,
+ RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V4SI,
RS6000_BTI_unsigned_V4SI, 0 },
{ ALTIVEC_BUILTIN_VEC_VPKSHSS, ALTIVEC_BUILTIN_VPKSHSS,
RS6000_BTI_V16QI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0 },
{ ALTIVEC_BUILTIN_VEC_VPKUHUS, ALTIVEC_BUILTIN_VPKUHUS,
@@ -4777,6 +4777,10 @@ const struct altivec_builtin_types
altivec_overloaded_builtins[] = {
RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0, 0 },
{ P8V_BUILTIN_VEC_VGBBD, P8V_BUILTIN_VGBBD,
RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0, 0 },
+ { P8V_BUILTIN_VEC_VGBBD, P8V_BUILTIN_VGBBD,
+ RS6000_BTI_V16QI, 0, 0, 0 },
+ { P8V_BUILTIN_VEC_VGBBD, P8V_BUILTIN_VGBBD,
+ RS6000_BTI_unsigned_V16QI, 0, 0, 0 },
{ P9V_BUILTIN_VEC_VINSERT4B, P9V_BUILTIN_VINSERT4B,
RS6000_BTI_V16QI, RS6000_BTI_V4SI,
@@ -5038,11 +5042,6 @@ const struct altivec_builtin_types
altivec_overloaded_builtins[] = {
{ P8V_BUILTIN_VEC_VUPKLSW, P8V_BUILTIN_VUPKLSW,
RS6000_BTI_bool_V2DI, RS6000_BTI_bool_V4SI, 0, 0 },
- { P8V_BUILTIN_VEC_VGBBD, P8V_BUILTIN_VGBBD,
- RS6000_BTI_V16QI, 0, 0, 0 },
- { P8V_BUILTIN_VEC_VGBBD, P8V_BUILTIN_VGBBD,
- RS6000_BTI_unsigned_V16QI, 0, 0, 0 },
-
{ P9V_BUILTIN_VEC_VSLV, P9V_BUILTIN_VSLV,
RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI,
RS6000_BTI_unsigned_V16QI, 0 },
--
1.9.1
