These two patches to fix PRs 78602 and 78560 fix aspects of the vector set and
extract code I've been working on in the last couple of months.
The two symptoms were essentially the same thing, one on vector set and the
other on vector extract. The core issue was both set and extract did not
verify an argument that should have been in a register, actually was in a
register, and generated code that raised an insn not found message.
PR 78602 was an error that I found in working with the next set of patches for
vector extract, where it would generate the insn not found message if the test
cases were compiled without optimization. The solution was to call force_reg
if the element number wasn't a register or constant.
PR 78560 was the opposite, in that it was on vector set, and it showed up with
-O3 optimization level. Like 78602, the answer was to call force_reg to force
the value being set into a vector element into a register.
Once the initial bug in 78560 was fixed, a secondary bug reared its head, in
that the calculation for the elment being set was a bit offset, when instead it
should have been a byte offset. The assembler complained when the offset field
was not between 0..15.
I have done full bootstraps and make check with no regressions on a little
endian power8 (64-bit only), a big endian power8 (64-bit only), and a big
endian power7 (both 32-bit and 64-bit). Cann I install both patches to the
trunk?
2016-11-29 Michael Meissner <meiss...@linux.vnet.ibm.com>
PR target/78602
* config/rs6000/rs6000.c (rs6000_expand_vector_extract): If the
element is not a constant or in a register, force it to a
register.
2016-11-29 Michael Meissner <meiss...@linux.vnet.ibm.com>
PR target/78560
* config/rs6000/rs6000.c (rs6000_expand_vector_set): Force value
that will be set to a vector element to be in a register.
* config/rs6000/vsx.md (vsx_set_<mode>_p9): Fix thinko that used
the wrong multiplier to convert the element number to a byte
offset.
--
Michael Meissner, IBM
IBM, M/S 2506R, 550 King Street, Littleton, MA 01460-6245, USA
email: meiss...@linux.vnet.ibm.com, phone: +1 (978) 899-4797
Index: gcc/config/rs6000/rs6000.c
===================================================================
--- gcc/config/rs6000/rs6000.c (revision 242972)
+++ gcc/config/rs6000/rs6000.c (revision 242973)
@@ -7257,6 +7257,8 @@ rs6000_expand_vector_extract (rtx target
convert_move (tmp, elt, 0);
elt = tmp;
}
+ else if (!REG_P (elt))
+ elt = force_reg (DImode, elt);
switch (mode)
{
Index: gcc/config/rs6000/rs6000.c
===================================================================
--- gcc/config/rs6000/rs6000.c (revision 242973)
+++ gcc/config/rs6000/rs6000.c (working copy)
@@ -7105,6 +7105,8 @@ rs6000_expand_vector_set (rtx target, rt
int width = GET_MODE_SIZE (inner_mode);
int i;
+ val = force_reg (GET_MODE (val), val);
+
if (VECTOR_MEM_VSX_P (mode))
{
rtx insn = NULL_RTX;
Index: gcc/config/rs6000/vsx.md
===================================================================
--- gcc/config/rs6000/vsx.md (revision 242968)
+++ gcc/config/rs6000/vsx.md (working copy)
@@ -2904,7 +2904,7 @@ (define_insn "vsx_set_<mode>_p9"
if (!VECTOR_ELT_ORDER_BIG)
ele = nunits - 1 - ele;
- operands[3] = GEN_INT (nunits * ele);
+ operands[3] = GEN_INT (GET_MODE_SIZE (<VS_scalar>mode) * ele);
if (<MODE>mode == V4SImode)
return "xxinsertw %x0,%x2,%3";
else
