On 9 September 2011 13:56, Richard Sandiford <richard.sandif...@linaro.org> wrote: > Ping for this patch:
>> This is the NEON part of the patch to handle address register writeback >> in the Cortex A8 and A9 schedulers. Although I can find no documentation >> to say exactly how this is handled by the pipelines, a latency of 1 >> does seem to work well in practice, and is much easier to implement. It sounds like this is good enough in practice. > > http://gcc.gnu.org/ml/gcc-patches/2011-08/msg01488.html > > which models address register writeback in the Cortex A8 and A9 NEON > schedulers. (Ramana has already approved the core equivalent, thanks.) I do have a one nit on the ml bit though I must say I'm not an ML expert which is why I resisted for a while. The one comment that I have and I should have realized earlier was that the file had been parameterized by the core in quite a few places and I would like to still retain that capability. This look better ? I have retained your original logic and only parameterized wblatency on the core . Thoughts ? Can someone else also give the ML bits a once-over ? It appears to generate identical descriptions to yours. cheers Ramana gcc/ * config/arm/neon-schedgen.ml (guard): Add Guard_writeback and Guard_writeback_only. (writebackLatency): New function. (collate_bypasses): Split hashtable insertion into a separate function. Add address writeback dependencies for load-store instructions. Use writebackLatency. Sort bypasses in order of decreasing latency. (guard_fn): Handle Guard_writeback and Guard_writeback_only. * config/arm/cortex-a8-neon.md: Regenerated. * config/arm/cortex-a9-neon.md: Likewise.
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