Segher Boessenkool schrieb:
On Wed, Nov 23, 2016 at 04:58:22PM +0100, Georg-Johann Lay wrote:
Hi, this causes an illegal code issue on avr.
Sorry about that.
[ snip ]
Trying 19 -> 7:
Failed to match this instruction:
(set (reg:HI 45 [ x+3 ])
(zero_extend:HI (reg:QI 25 r25 [ x+3 ])))
Successfully matched this instruction:
(set (reg:HI 45 [ x+3 ])
(and:HI (reg:HI 25 r25)
(const_int 255 [0xff])))
allowing combination of insns 19 and 7
R25 is a 16-bit hard reg, but HImode (and larger) registers must start
at an even register number.
So why does the define_insn allow it?
Because the insn predicate is register_operand:HI which should be fine
as it is non-strict RTL. Or are predicates supposed to reject such odd
operands the backend would never generate itself?
Are you saying that register_operand:HI is not correct?
IMO, if combine is playing with hard regs, it should be conservative and
not create new hard regs out of thin air... like
* Test HARD_REGNO_MODE_OK
* Don't increase HARD_REGNO_NREGS because it's not a good idea to create
hard regs out of thin air. On avr, for example, one should strive to
get to smaller modes, not to blow mode sizes...
Johann
Please open a PR so I don't lose track.
Thanks,
Segher
