Re: [PATCH, GCC/ARM] Fix ICE when compiling empty FIQ interrupt handler in ARM mode

[Kyrill Tkachov]

On 09/11/16 16:19, Thomas Preudhomme wrote:

Hi,

This patch fixes the following ICE when building when compiling an empty FIQ 
interrupt handler in ARM mode:

empty_fiq_handler.c:5:1: error: insn does not satisfy its constraints:
 }
 ^

(insn/f 13 12 14 (set (reg/f:SI 13 sp)
        (plus:SI (reg/f:SI 11 fp)
            (const_int 4 [0x4]))) irq.c:5 4 {*arm_addsi3}
     (expr_list:REG_CFA_ADJUST_CFA (set (reg/f:SI 13 sp)
            (plus:SI (reg/f:SI 11 fp)
                (const_int 4 [0x4])))
        (nil)))

The ICE was provoked by missing an alternative to reflect that ARM mode can do 
an add of general register into sp which is unpredictable in Thumb mode add 
immediate.

ChangeLog entries are as follow:

*** gcc/ChangeLog ***

2016-11-04  Thomas Preud'homme  <thomas.preudho...@arm.com>

        * config/arm/arm.md (arm_addsi3): Add alternative for addition of
        general register with general register or ARM constant into SP
        register.


*** gcc/testsuite/ChangeLog ***

2016-11-04  Thomas Preud'homme  <thomas.preudho...@arm.com>

        * gcc.target/arm/empty_fiq_handler.c: New test.


Testing: bootstrapped on ARMv7-A ARM mode & testsuite shows no regression.

Is this ok for trunk?

I see that "r" does not include the stack pointer (STACK_REG is separate from 
GENERAL_REGs) so we are indeed missing
that constraint.

Ok for trunk.
Thanks,
Kyrill

Best regards,

Thomas