Explicitly switch between the JR and JRC instructions for the table jump
in `casesi_internal_mips16_<mode>', depending on their availability in
the ISA level chosen, taking away the reliance on assembler relaxation.
Adjust the instruction count accordingly now that we control the length
of this code piece ourselves.
gcc/
* config/mips/mips.md (casesi_internal_mips16_<mode>):
Explicitly switch between JR and JRC for the table jump. Adjust
instruction count.
---
OK to apply?
Maciej
gcc-mips16-casesi-ret.diff
Index: gcc/gcc/config/mips/mips.md
===================================================================
--- gcc.orig/gcc/config/mips/mips.md 2016-11-12 10:57:13.000000000 +0000
+++ gcc/gcc/config/mips/mips.md 2016-11-12 10:57:30.158107981 +0000
@@ -6442,9 +6442,15 @@
output_asm_insn ("<d>addu\t%4, %4, %5", operands);
- return "j\t%4";
+ if (GENERATE_MIPS16E)
+ return "jrc\t%4";
+ else
+ return "jr\t%4";
}
- [(set_attr "insn_count" "11")])
+ [(set (attr "insn_count")
+ (if_then_else (match_test "GENERATE_MIPS16E")
+ (const_string "10")
+ (const_string "11")))])
;; For TARGET_USE_GOT, we save the gp in the jmp_buf as well.
;; While it is possible to either pull it off the stack (in the
